Thank you for your interest in working with LTSpice via this blog post. I will fill you in on my own experiences and perhaps this will trigger some new ideas for you. From your question, I think you have downloaded myflip-flop gates described in this post. I also assume you have tried to extend their use beyond my simple test bed.

I went through a learning curve in the use of LTSpice supplied logic gates. I had already confirmed with other LTSpice online users that the basic building blocks for my own mixed analog/digital designs can and should start with these basic building blocks. At first I thought all basic gates supplied with the LTSpice library are created “equally” - in the sense that each flip-flop behaves like a collection of generic similarly behaved set of gates as defined in some of my digital logic text books. This turns out not to be true.

Some LTSpice library gates are better choices than others based on the actual performance of the logic gates within the simulator. I discovered that the worst flip-flop gates to start with are included within the SR Flip-Flop and the best ones are in the D Flip-Flop. This is why, in my final design, I selected the D Flip-Flop even to meet SR Flip-Flop design requirements. See my last photo in this post.

I more fully explore the subject in my next post here: http://www.embeddedcomponents.com/blogs/2008/04/74hc193-for-ltspice-switchercadiii/

In the 74hc193 blog post, I describe a more complex circuit built from many of my basic flip-flops along with some controls to simulate more specific real-time behavior constraints via the .param and .tran statements: See figure #2 {larger view} as a detailed example. The .param control works as a global set of controls because I included these same variable names within each gate of my sub-assemblies.

Does this help?

Best regards,

Ron

Embedded in a mixed analog and power model these logic functions fail to perform. I did a side-by-side with the SR Flop for example, and given the same input and output characteristics with a very, very simple demo circuit and my more complex application.. the SR Flop in the more complex application failed. Any Ideas???

Allen Kelly, Northrop Grumman

Best regards,
Ron

It’s more safe to make JK- and T-flipflops based on the A-device dflop (D-flipflop). This dflop is already only edge sensitive as required.

You can find the examples in the Files-section of the LTspice group.
Files > Lib > JK-Flipflop and T-Flipflop

Best regards,
Helmut