Archive for the 'Component Projects' Category

Dual-Channel Digital Volume Control Circuit Simulation

Wednesday, January 11th, 2012


Ron Fredericks writes: In today’s post, I will demonstrate the value in using LTspice to simulate a complete circuit.

In several previous LTspice posts I described how to use the simulator as a test jig for single IC’s and gates. Each block in a circuit should be tested within LTspice before creating a multi-circuit simulation to verify performance against expected results. The test jig process included downloading a custom gate, IC, and spice code for the cd4066 bi-polar analogue switch from the yahoo LTspice user group, and the creation of my own 74LS193 pre-setable up/down counter from primitive logic gates. Ltspice is very flexible. Most discrete components are readily available in the library, with a great support group from on yahoo. There are a wide variety of spice and pspice models to important from many Internet sources as well..

The Circuit to Simulate

I came across this digital volume control circuit during a web search. The circuit seems to be fairly popular as it shows up in thousands of places on the web. I thought it would be a good place to start my investigation of digital volume control even though there are many industry specific chips out there to manage some of these functions as well as chips that offer much larger feature sets. With this circuit I hope to expand on the features to create new volume control and measurement circuits – perhaps while investigating the value in using an more advanced volume control chip.

This circuit could be used for replacing your manual volume control in a stereo amplifier. In this circuit, push-to-on switch S1 controls the forward (volume increase) operation of both channels while a similar switch S2 controls reverse (volume decrease) operation of both channels.
Here IC1 timer 555 is configured as an astable flip-flop to provide low-frequency pulses to up/down clock input pins of pre-setable up/down counter 74LS193 (IC2) via push-to-on switches S1 and S2. To vary the pulse width of pulses from IC1, one may replace timing resistor R1 with a variable resistor.

Operation of switch S1 (up) causes the binary output to increment while operation of S2 (down) causes the binary output to decrement. The maximum count being 15 (all outputs logic 1) and minimum count being 0 (all outputs logic 0), it results in maximum and minimum volume respectively.

The active high outputs A, B, C and D of the counter are used for controlling two quad bi-polar analogue switches in each of the two CD4066 ICs (IC3 and IC4). Each of the output bits, when high, short a part of the resistor network comprising series resistors R6 through R9 for one channel and R10 through R13 for the other channel, and thereby control the output of the audio signals being fed to the inputs of stereo amplifier. Push-to-on switch S3 is used for resetting the output of counter to 0000, and thereby turning the volume of both channels to the minimum level. — Sheena K. for electronicsforu magazine

Dual-Channel Digital Volume Control Circuit (click to enlarge)

The LTspice Simulation

The Circuit

Volume Controller Schematic in LTspice (click to enlarge)

The Simulation Results

LTspice Simulation Results (click to enlarge)

Simulating the CD4066 Quad Bilateral Switch With LTspice

Monday, December 12th, 2011


Ron Fredericks writes: Today is Robert Norton Noyce’s birthday (born 12/12/1927) – co-inventor of the integrated circuit (IC). So I thought I would take a few minutes and document my work modeling the CD4066 quad bilateral switch with the LTspice simulator.

In this post I describe how flexible LTspice can be as a general SPICE circuit simulator, and how accurate its behavior can be in comparing LTspice test results with the physical IC’s datasheet. In this example I use the CD4066B as the IC to model. I test the model using its characteristic “on” resistance curves under various voltage and current operating conditions. I conclude by using a standard CD4066 datasheet to verify the accuracy of the model.

Meanwhile this is the last IC I need to simulate the analog section of the digital volume control circuit using LTspice I mentioned in two of my previous blog entries:

Define one of four bilateral switches on CD4066 for LTspice

 

To get the CD4066 IC into my circuit simulation, I first created a symbol for one of the four bilateral switches in this package, and defined a SPICE subcircuit definition for the switch using existing SPICE CD4007 gate models as the starting point.

Symbol for one of four bilateral switches on the CD4066 IC

 

LTspice symbol for one of four bilateral switches on cd4066 (click to enlarge)

LTspice Subcircuit Definition for CD4066
Note the LTspice implementation of the SPICE language is highlighted (below) using my own GeSHi language highlighter library with key sections of the language (.model and .subcircuit) hyper-linked into SPICE language definitions that I have created on the contributor pages of this website. SPICE is a difficult language to highlight using GeSHi because many of the SPICE language constructs are so short that they overlap with longer language constructs. I plan to add more language definitions in the future as my circuit models need them, and I continue to find unique look-up algorithms to match GeSHi language highlighter categories.

 

code=ltspice
  1.  
  2. * CD4066 Analog Switch
  3. * SYM=CD4066
  4. * Transistor models are from LTspice group member kcin_melnick
  5. * See message number 16897, http://tech.groups.yahoo.com/group/LTspice/
  6. * Analog Switch Control In Out Vdd Vss
  7. .SUBCKT CD4066 2 11 4 10 7
  8. X1 2 6 10 7 INVERT
  9. X2 6 1 10 7 INVERT
  10. M1 14 6 7 7 CD4007N
  11. M7 11 6 14 10 CD4007P
  12. M3 11 1 14 14 CD4007N
  13. M4 11 1 4 14 CD4007N
  14. M8 11 6 4 10 CD4007P
  15. .SUBCKT INVERT 1 2 3 4
  16. * Inverter In Out Vcc Vss
  17. M1 2 1 3 3 CD4007P
  18. M2 2 1 4 4 CD4007N
  19. .ENDS
  20. .MODEL CD4007N NMOS (
  21. + LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m
  22. + RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p
  23. + PB=.8 TOX=1200n)
  24.  
  25. .MODEL CD4007P PMOS (
  26. + LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m
  27. + RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P
  28. + PB=.8 TOX=1200N)
  29. .ENDS

Testing the CD4066 Circuit in LTspice

Finally, I dragged the symbol with subcircuit models into my LTspice program and ran a series of tests to demonstrate the “on” resistance characteristics associated with the switch at various voltage and current values. Note the multicolored graph showing the resistance curves at various VI levels.

 

VI curves and circuit schematic for cd4066 bilateral switch under test (click to enlarge)

Get these files from LTspice Yahoo Group

The 4 main files used to create this demo circuit can be obtained from LTspice Yahoo Group. Special thanks to Helmut Sennewald

See the figure below…

LTspice Yahoo Group File List (click to enlarge)

Comparison of LTspice circuit simulation with datasheet

The TI datasheet compares favorably with my simulations. The LTspice “on” resistance curves and values are nearly exactly the same as those shown in figures 2,3, and 4 of TI’s datasheet (page 6) for the range I tested.

At this stage of development in simulating the analog path for my automatic volume control circuit, I see that the “on” resistance curve may create an unstable signal path under normal audio conditions unless the operating voltage (Vcc ) is much higher than the original circuit’s proposed 5 VDC power supply.

References

Linear Technologies LTspice Landing Page

Texas Instruments datasheet for the CD4066B

What’s All This CD4007 Stuff, Anyhow?
Bob Pease | ED Online ID #6073 | April 5, 1999
http://electronicdesign.com/Articles/ArticleID/6073/6073.html

Fault in CD4066 Model
kcin_melnick | LTspice Yahoo Tech Group Message #16897 | June 24, 2007
http://tech.groups.yahoo.com/group/LTspice/message/16897

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Introduction to Google Android

Friday, February 5th, 2010


Ron Fredericks writes: Are you new to the google android smartphone platform and developer ecosystem? If so, then this online video produced from LectureMaker’s high-tech video studio can help you get up to speed very quickly. The video includes several navigation dots along the time line so you can jump to the content you want to watch (once it has downloaded). Expect to get an overview, some sample code demos, and an understanding of the business case behind developing apps for Android from watching this great video presented by Marko Gargenta of Marakana.

Enjoy…

Android Introduction by Marko Gargenta, marakana
Presented by Peter Lam, Mobile SIG Co-chair, Software Developer Forum

Video Link

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Introducing 74HC193 Simulation to LTspice

Monday, April 21st, 2008

Ron Fredericks writes: I have completed the design and test of a new component for LTspice/SwitcherCAD III circuit simulation and schematic capture. In a previous post I discussed my interest in the 74193 presettable synchronous 4-bit binary up/down counter IC for a digital volume control circuit I am building. The circuit simulation described below focuses on how to simulate the 74HC193 IC, but timing and voltage parameters built into this design allow a designer to easily simulate other variants of this IC from high speed Si-gate CMOS HC and HCT devices to low power Schottky TTL devices.

All circuits related to this 74HC193 simulation are available here>

The 74HC193 Component

See figure 1 below for a screen shot of the completed design. The circuit was built from the digital gates in the component library supplied with the original Linear Technology’s free LTspice tool.

74HC193 Circuit and Related Components
Figure 1 – 74HC193 Circuit and Related Components
View larger image>

To keep the design looking like the original data sheet logic diagram, as published by companies that include NXP Semiconductors and Texas Instruments, a custom “T notS-R FlipFlop” subcomponent and corresponding assembly file was first created. This subcomponent was reused 4 times in the main IC logic diagram. An assembly file called 74hc193.asy was also created. It includes all pins used on the commercial IC except ground and Vcc. The IC’s internal power supply is not simulated by the Linear Technologies’ gates, and so they are not used or required in this design either.

Each gate within the design has a few variables assigned to them so that the IC remains flexible and easy to reuse in new projects:

  • tdgate right td (propagation time delay assigned to each gate)
  • tdgate2 right td (propagation time delay assigned to the D FlipFlop)
  • tripdtgate right tripdt (td’s accuracy band assigned to each gate including the D FlipFlop)
  • vhighgate right logical high value for each gate and D FlipFlop
  • vlowgate right logical low value for each gate and D FlipFlop

These variables can be assigned their corresponding time and voltage values using a .param statement placed in the main circuit. These values are then within scope for automatic reuse by the 74HC193 component and flipflop subcomponent simulations. Below is an example of how parameter assignment can be made (as used in the test circuit described next):

.param tdgate=10n tdgate2=3*tdgate tripdtgate=1n vhighgate=5v vlowgate=0v

(more…)

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New Gate Design Using LTspice/SwitcherCAD III

Tuesday, April 15th, 2008


Ron Fredericks writes: recently I discovered that I was going to have to create my own IC component and symbol for my on-going digital volume control circuit simulation. My first step was to check in with the LTspice forum on yahoo groups. On the forum I requested any previous design for the IC I needed. I also asked the group’s readership if they thought it was correct to build a new IC from existing low level digital gates – gates that are already supplied with the LTspice distribution by Linear Technologies.

Well, I did not find a previous inventor for my IC simulation, but I did get confirmation that the gate build-up was a common strategy. And, this same forum engineer supplied me with a copy of an IC simulation of his own – one very similar to my IC requirement – he supplied a symbol and sample test bed to accelerate my learning curve. Here is a link to my support dialog.

I would like to thank Helmut Sennewald for his time and excellent service to the LTspice yahoo forum. It is his effort and many others who make this forum such a valuable community resource. This forum in turn, has made the LTspice/SwitcherCAD III circuit capture and spice tool a viable design tool for many embedded component users and EE designers.

Introducing the T S-R Flip-Flop

To build my new IC, I had to build a new digital logic block. This component is a Toggle Flip-Flop with Set and Reset functions added. In this blog post I introduce my readers to this new component and share the simulation circuit for others to use and learn from.

See the figure below for an initial design of the T S-R Flip-Flop, including a truth table in the form of a waveform diagram, the circuit, a pulse detector sub-circuit and their related assemblies. This circuit is just an initial design because it uses an S-R Flip-Flop and a simple pulse detector sub-circuit for its clock.

T S-R Flip-Flop and releated sub-circuits and assemblies

View larger image>

Final Design for the T S-R Flip-Flop

This section of my post is an update, thanks to a review by Helmut Sennewald. See figure below for my final design of the Toggle S-R Flip-Flop. This design overcomes two problems in my initial design, both resolved by starting with the D Flip-Flop with its built-in clock. The reuse of this more full-featured LT supplied component in my design eliminated the home-brew pulse maker sub-circuit. And in so doing, the slower S-R Flip-Flop. Slower because I had to set the SpiceLine time delay to a minimum of 20 nanoseconds (or td >= 2x the gate time delay) to support the simulation of my simple pulse maker sub-circuit. The D Flip-Flop has an internal clock so I could eliminate the pulse maker sub-circuit. End result: one less sub-circuit and faster Flip-Flop simulation using a time delay set to a minimum of 10 nanoseconds (or td >= 1x the gate time delay).

T S-R Flip-Flop (final design)

View larger image>

Download

To test my knowledge of digital design using the LTspice tool, I created a number of similar flip-flop components which are included in the download:

  1. S-R Flip-Flop test circuit
  2. S-R Flip-Flop with Enable gate and test circuit
  3. S-R Flip-Flop with rising edge clock and test circuit
  4. J-K Flip-Flop with rising edge clock and test circuit
  5. D Flip-Flop with Enable gate and test circuit
  6. T S-R Flip-Flop from S-R Flip-Flop and test circuit (initial design)
  7. Rising Edge Pulse Detector (not high performance design)
  8. T S-R Flip-Flop from D Flip-Flop and test circuit (final design)

Download the components listed above for your LTspice designs all in one zipped directory.

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Simulating the 555 IC with LTspice

Wednesday, March 26th, 2008


Ron Fredericks writes: I was designing a simple CMOS timer circuit around a 555 chip this evening. It might be the heart beat for a new digital volume control I have been thinking about. Normally I look for my breadboard and parts box but this time I thought I would try out Linear Technologies LTspice/SwitcherCAD III workbench instead.

SwCAD III First Time Use

The tool is free and comes with a lot of support. I downloaded the software and installed it very easily on my Windows XP PC. It includes a graphical schematic design tool with lots of ready made simulated components, including an NE555 for my initial project. Designing the circuit with the built-in CAD tool works very intuitively. While the LTspice simulation took a bit of head scratching before it worked for me.

I was able to configure and run the simulation using the drop down tools menu and the little “running person” icon on the tool bar. But all I could get out of the simulation was a black screen with voltage and timing ticks along the left and bottom edges. So my first problem was in realizing that the visual display would remain black and traceless until I put the mouse cursor over a wire then click. When the little instrument probe showed up as my mouse icon, I realized what was going on here. With the mouse click, waveform tracings would appear in the black panel.

My second problem was that the circuit would not oscillate. Not good for an oscillator design. First, I forgot to connect the 555’s threshold + trigger pins to the R2-C2 node using the wire tool. But still no oscillation, just flat line traces were observed. Now I already know that getting circuits to oscillate follows Murphy’s Laws: Oscillators remain stable, Amplifies and Buffers oscillate, whenever possible. I found a note on the Old School Hacker blog with a fine solution. You must simulate the circuit with a power supply starting from 0 volts rather than just have an instant on Vcc power supply.

In hind sight dah, its the initial transient response from the circuit’s components that kicks the oscillator into oscillating.

After a little practice I improved the schematic diagram with the use of named nodes and seperation of the temporary load resistors R3 and R load from the more permanent circuit components. The load resistors are just place holders for a real load to be added to the circuit schematic next. Look for my next blog post on this subject.

Finally, I used the cursor measurement facility built into the LTspice window (trace window). With this feature, I was able to make “real” measurements on the waveform for frequency and duty cycle.

Circuit

Here is what I was able to generate using the LTspice/SwitcherCAD III tool:

LTspice/SwitcherCAD III circuit diagram and waveforms

View larger image>
Download 555 Astable Flip-Flop Schematic Circuit Diagram>

Referring to the figure above:
   Green Trace -> Output (IC 555 pin 3)
   Blue Trace -> Trigger / Threshold (IC 555 pins 2 & 6)
   Red Trace -> Discharge (IC 555 pin 7)

The Astable Multivibrator

The circuit shown above will trigger itself and free run as a multivibrator. The capacitor C2 charges through resistors R1 and R2 yet discharges through R2 only. Thus, the duty cycle (D) may be precisely set by the ratio of these two resistors. The capacitor charges and discharges between 1/3 Vcc and 2/3 Vcc. But the initial pulse charges C2 starting from 0 Vcc and so this first pulse duty cycle is unique. Since the charge rate and the threshold levels are directly proportional to the supply voltage Vcc, the frequency of oscillation (f) is independent of the supply voltage.

Frequency Calculation Duty Cycle Calculation
   
f = 1.38/{(R_1 + 2R_2)C_2} D = {tau}/T = {R_1 + R_2}/{R_1 + 2R_2}
   
1.7 hertz=1.38*10^3/{(150 + 2*332) ohm farads} 0.59~={150 + 332}/{150 + 2*332}
   
Measured = 1.8 hertz Measured = 0.60
   
Where:
    f is frequency in hertz
    C is capacitance in farads
    R is resistance in ohms
Where:
    D is duty cycle
    tau is non-zero output duration
    T is the period of the output
    R is resistance
   

Reference

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ROI as an Effective Communications Tool for Engineers

Wednesday, September 26th, 2007

Abstract

Ron Fredericks writes: Engineers want to build compelling products that meet their project requirements. Corporate executives want to invest in innovative people that build products that, in turn, meet their market’s window; while, both want to stay within budget. Yet both groups may feel overwhelmed with the prospect of expressing the very heart of their inspiration at some critical times during the life of these projects. In today’s post, I try to address this issue from the engineer’s perspective reaching out to the financial decision makers that ultimately control the purse strings of every project.

Table of Contents

Introducing Financial-Speak to Engineers
ROI Example: Embedded Linux
Evaluating Incremental Cash Flows
ROI Example: Simple Project Comparisons Using Net Present Value
ROI Example: Evaluating an Infrastructure Project
ROI Example: The Original Design Manufacturer
References
Errors and Changes Planned for this Blog Post

Introducing Financial-Speak to Engineers

In a previous post I introduced the idea that ethics might be the common framework between this dichotomy in communication between engineers, marketers, and executives. In this post, I suggest that engineers might apply this ethical approach by taking some time out to learn the language of business development from a financial management perspective – a conversational framework suitable for an interdisciplinary team concerned with engineering risk and strategic business value, but expressed using financial definitions.

The term Return On Investment (ROI) can be used for all three disciplines: engineering, marketing, and finance. ROI is just vague enough to cover most any discussion an engineer may encounter through-out the life of a project: from the initial decision to fund your project, to evaluating change requests during the design, build, test, and deployment cycle of an ongoing project. Evaluating ROI from a financial perspective is an ethical approach to decision-making because the financial terms I promote for this ethical framework have very precise meanings. So precise in fact, that I too have had to go back and rewrite several sections of this blog post thanks to One Nomad’s Blog comments received in this blog’s first posting.

It was the lack of financial precision embedded within my first draft for this blog post which my guest reader used to convince me of my own mistakes. Yet to be clear, identifying my mistake is also my gain. Effective communication is a process of two or more people sharing ideas…

Learning to converse and plan using financial terms for ROI decision-making can level the playing field between engineers, marketers, and business executives since ROI itself is not a common financial term. Engineers practicing Financial-Speak centered around ROI as the goal, can help reduce many of the common problems related to individuals trying their best to participate in team decision making. This leveling of the playing field – between team members – can also enhance the power of their conversation, leading the way for the much sought after innovations that are in popular demand today.

Consider building a financial model around ROI before presenting your most important technical needs to executives, marketers, and other decision makers. Read on to learn how. Of course ROI from a financial perspective is not the only way to build effective interdisciplinary teams with engineers involved. In a future post I may suggest a corollary to this ethical approach for executives and marketers who would like to reach out to engineers – using Six Sigma, CMMI, and emerging techniques developed by Dr. Thomas J. Buckholtz as useful processes seeped in ROI terminology.

Figure 1: Net Present Value Equation

NPV(CF_k, R, IV) := IV + sum{k=1}{N}{CF_k / (1+R)^k }

Where:
NPV is the Net Present Value function, in dollars
CF is a project’s Cash Flow, in dollars
R is the hurdle Rate, in percent per period
IV is the Initial Investment (a negative number), in dollars
And:
k is the cash flow’s time increment, or period
N is the total number of cash flow periods for k
Time increment for CF and R might be in years, quarters, or months, for example

ROI Example: NPV’s Effect on Embedded Linux

The equation in Figure 1 forms the heart of my “ethics in engineering” proposal. Namely, the sooner a new device gets to market, the sooner a firm can realize new income. New income realized sooner, is much better than income realized later. A finance discussion around NPV would call this time’s negative impact on the value of money. I’m talking about the exponential effect that the prevailing interest rate, R, has in the NPV equation shown in figure 1.

A few years ago several of the leading embedded operating system suppliers used this equation to show that embedded Linux was a poor choice for new embedded device development projects. One such paper published by Dr. Jerry Krasner in 2003, Total Cost of Development, presents the typical argument pretty well. At that time Dr. Krasner and many others may have been right. Now in 2007, times have changed significantly. A recent blog entry on CNET shows the missing element from Dr. Krasner’s report and is a Harold for the embedded industry going forward: Oracle touts Linux deals.

How times have changed…

Because of the significant adoption of Linux in enterprise projects, the total project cost of using embedded Linux has gone down too. Indeed, the migration and reuse of enterprise Windows operating system application programming interfaces (API’s), kernel components, and development tools into embedded device projects was a key part of Dr. Krasner’s report, see link above. Dr. Krasner concluded at the time that embedded Windows CE made the best choice for new projects from a total cost of ownership perspective – just another way of looking at NPV!

Now the ROI benefits behind projects that select embedded Linux follows Dr. Krasner’s logic perfectly. Embedded Linux is now experiencing the same reduced total cost of ownership that only embedded Windows CE enjoyed just a few years ago. The reduced total cost of ownership comes from new and improved tools, components, and API’s that cross over from enterprise projects to the embedded marketplace. There is a significant overlap in Linux kernel updates, components, and tools driven by enterprise projects that are also suitable for use in embedded projects.

The available pool of engineers that know how to work with Linux can now support embedded development projects that use embedded Linux too. The marketing movement around the value and excitement of using Linux may also reduce the cost of taking an embedded device to market. In short: lower upfront costs, more options, more solutions, and faster time to market. Even Dr. Krasner has decided to post an update to his old white paper showing total cost of development to be favorable for embedded Linux projects. Download his updated paper.

None of these enterprise driven benefits exist with respect to the traditional embedded real-time operating system (RTOS). To be clear, there are other benefits to using an RTOS. I discuss one significant benefit to using an RTOS in another post: How to Leverage the Value of a Board Support Package.

Evaluating a Project’s Incremental Cash Flow

NPV is just one example of applying the principle of ROI to making project decisions. NPV falls into the general category of capital budgeting, a process of evaluating proposed investments into new projects. The capital budgeting process is concerned only with incremental cash flows. So the vague concept of ethics can be transformed into a specific financial discussion.

Two financial functions can measure time’s effect on money:

(1) Net Present Value (NPV) expressed as a monetary value,
and

(2) Internal Rate of Return (IRR) expressed as a percentage.

Where:

Net Present Value (NPV) of a capital budgeting project is the dollar amount of change in the value of the firm as a result of undertaking the project [Ref: Financial Management: Principles and Practice P.234]. The mathmatic definition for NPV is:

NPV(CF_k, R, IV) := IV + sum{k=1}{N}{CF_k / (1+R)^k }

Where:

IV = Initial Investment (a negative number)
CF_k = cash flow value (project outputs – project inputs) for period k
R = hurdle rate per period, where period is a unit of time, typically year, quarter, or month
N = total number of periods for the project

Present Value (PV) is the value today of a future, or expected, cash flow. The mathematic definition for PV is:

PV(CF_k, R)  := sum{k=1}{N}{CF_k / (1+R)^k }

NPV can be expressed in terms of its present value (PV):

NPV = IV + PV

Hurdle Rate is the required rate of return before launching a new project. The hurdle rate must be carefully chosen. It can be expressed as a percent per period. The period is commonly defined as one year, but other convenient time period could be selected such as one quarter, or one month. The same unit of time will need to be associated with cash flow. Other rate terms can be used in addition to, or instead of, hurdle rate: discount rate, cost of capital, or interest rate.

Internal Rate of Return (IRR) is the discount rate at which the
NPV of the project is zero
. [Ref: Financial Management: Principles and Practice P.240]. The mathematics definition for IRR is related to NPV:

0 := IV + sum{k=1}{N}{CF_k / (1+IRR)^k }

NPV and IRR are related to each other:
What follows is a list of relationships between NPV and IRR. Use these relationships after calculating the NPV and IRR for each of the proposed project alternatives.

(1) If NPV(CF, R, IV) = 0,
then the hurdle rate, R = IRR

(2) For any set of cash flows estimated for a prospective project,
there is only one value for NPV.
But, the same project model can result in several IRR values,
where NPV = 0.

(3) If IRR > Hurdle Rate,
then a prospective project may make an acceptable
investment.

(4) If IRR >> Hurdle Rate (i.e. significantly greater than),
then a prospective project may carry too much risk.

(5) The hurdle rate includes both a minimum desired rate
of return for a project, and a threshold representing risk.
(5-a) A typical hurdle rate for an E-Business project
might be 15%.
(5-b) A typical hurdle rate for an embedded systems project
might be 18%.
(5-c) Embedded Components, Inc. is focused on lowering risk
for its members by promoting the re-use of pre-existing
components through its online marketplace
for embedded device manufacturers and their
communities.

(6) In general seek to maximize NPV, not IRR.

(7) Yet, if two projects have NPV curves that cross over each
other,
then the interest R where the curves cross is called
the Crossover Point.
(7-a) If the Crossover Point > IRR,
then accept the project with higher NPV.
(7-b) If the Crossover Point <IRR,
then accept the project with higher IRR.

(8) An NPV value of zero also means the investment into that
project would neither gain nor loose value for the company.

(more…)

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An Introduction to the HHP-16K EPROM Emulator

Sunday, September 9th, 2007


Ron Fredericks writes: The HHP-16K EPROM Emulator allows application code to be read by Hewlett-Packard’s (HP’s) HP-41 calculator. Instead of inserting a small pre-built module into one of the four module bays of the calculator, such as the PPC ROM module discussed in one of my previous blog posts, this unit allows a person to use custom built programs previously stored into EPROMs (Erasable Programmable Read Only Memory devices) using software development tools and an EPROM burner.

Figure 1: HPP-16K Emulator Connected to HP-41 Calculator

HPP-16K EPROM Emulator connected to HP-41 Calculator
Photo by Ron Fredericks using Canon EOS-10D 34mm fluorite lens, UV Filter, 1.5s & f/22 @ ISO 100, on tripod, from Embedded Components’ HP lab collection.

Business Development using EPROM

The HHP-16K represents, a stepping-stone from source code to mass marketing through the use of HP’s commercial software development tools and it’s professional services team. Advertisement and promotion of HP’s professional services to productize HP ROM modules from EPROMs could be found within HP’s own software development tools, and in newsletters — newsletters published by HP and by independent self-assembling developer communities such as national and international versions of the HP Computing Club or HPCC.org. HP’s fee for this service was not trivial, often HP computer clubs would collect donations from 100’s or 1000’s of their members to raise the $20,000 to $60,000 (in 1980’s dollars) to produce these ROM modules for their members – all before the Internet.

This emulator is an example of an important design pattern for modern day software developers forming into ecosystems around mass marketed smart consumer devices!

A typical consumer device in today’s market often has gigabytes of flash memory or other extensions via cellular networks, enterprise networks, or WI-FI Internet access, that behave just like this old 16 kilobyte emulator. With this design pattern – developers can improve the consumer’s experience on popular devices by adding new software applications, middleware, content, and development tools. While at the same time, developers gain significant new business development opportunities for themselves, content providers, software tools vendors, professional services teams, and device manufacturers alike.

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How to build Dean Lee’s Syntax Highlighter from latest components

Tuesday, May 29th, 2007

Ron Fredericks writes: In my last two posts:

During my research to solve the word wrap problem, I discovered a few more issues leading me to update Dean’s plugin with the latest version of GeSHI (an open-source project: Generic Syntax Highlighter for php. Highlight many languages, including PHP, CSS, HTML, SQL, Java, Assembler, and C for XHTML compliant output) and removal of unused files. I thought other WordPress bloggers might like to take advantage of the latest code too, so I document the steps needed to build a clean plugin with the latest components.

Flow Chart / Swim Lanes Widget
Below is a Flash widget I built to document the steps needed so you can roll your own up-to-date plugin. Follow these steps and you won’t have to be a programmer to get the benefits from the latest versions of these program components. The widget actively links to the latest PHP files and CSS classes:

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Community Software Development for Embedded Devices

Wednesday, April 4th, 2007


HP-41CX mobile computer/calculator with community developed PPC ROM software applications and synthetic code library
Photo by Ron Fredericks using Canon EOS-10D 34mm fluorite lens, circular polarizer, 1.5s & f/22 @ ISO 100, on tripod, from Embedded Components’ HP lab collection.

Ron Fredericks writes: I envision the day when community software engineering projects are commonplace for embedded devices. Like the PPC ROM demonstrated back in 1981.

What follows is a review of the PPC ROM community development project – a first for smart mobile devices, then an offer to help others in moving this great body of open source professional tools to modern devices: comment on this post if you are interested in this project or in community development of software for embedded devices in general.

Wouldn’t it be nice to have powerful new applications built on top of our routers, digital recorders, HDTV’s; or even industrial process monitor and control systems, or lab instruments; hey how about our cars and public transport vehicles? No I don’t mean that you buy a new device or car with new applications pre-loaded by the device manufacturer and shipped with the soon to be obsolete device – I mean groups of experts organizing into communities with other experts to design, develop, test, document, package, and deliver new software solutions onto devices for their own members’ sales channels. Does this sound far fetched?

Community development around open-source software such as Java, the Linux operating system, or Mozilla’s Firefox web browser have emerged as reusable project management solutions to complex software engineering issues – See Asa Dotzler’s Job Morph: Herding Cats to see how Mozilla motivates workers who aren’t actually on the payroll.. So I know the engineering community is ready for a new challenge – one that has already been solved back in 1981 – one that affects the speed of technology reuse around the globe today.

Development for today's embedded/mobile devices has many similarities to the HP-41 personal programmable calculator
Photo by Ron Fredericks using the same settings as the previous photo, of his favorite mobile smart device.

So let me share with you a project I recently discovered. It’s embodied in a user’s manual published in 1981 by a community of engineers – no, not your typical product manual ticked out on a company payroll. The forward describes a first-of-its-kind effort behind this user manual, and the embedded software it documents. The author expresses his excitement in being part of the “first community developer” project for a smart mobile computing device and it is so similar to the smart devices we use today! Did I mention that Linux, or even community networks like web and email didn’t exist back then? How did they do it? Can we learn from their effort and apply this community project, or its method, for today’s embedded devices? I think the answer is yes – with a little help from the embedded operating system suppliers’ communities and some innovative hardware device manufacturers. The embedded operating system, software community project management, and smart device platforms have come to a wonderful cross-road that truly supports community software development as a ripe low-hanging opportunity for us today.

The forward to this 500 page user manual describes the struggle and accomplishment of 100 developers who formed their own community project to develop a “ROM” or read-only memory module they called a “PPC ROM” that plugs into an HP personal computer that is now 25 years obsolete called an HP-41. The “PPC” reference is to the names – Personal Programmable Calculator, or Personal Programmer’s Club, or Prolific and Productive Computing – as well as the PPC Calculator Journal that was the herald for the HP calculator’s developer community back in the day. Similar to the commonplace e’zines we read, or get spammed with today. But different because the taxonomy created by today’s almost endless stream of eBlasts, tagged content, blogs, forums, and RSS feeds by themselves don’t create an engineers’ sense of community. The spontaneous motivation to organize into a sense of community requires a mood that has only been created by a real person – a person that shifts a group of developers’ paradigm . (more…)

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