All circuits related to this 74HC193 simulation are available here>

The 74HC193 Component

See figure 1 below for a screen shot of the completed design. The circuit was built from the digital gates in the component library supplied with the original Linear Technology‘s free LTspice tool.

Figure 1 – 74HC193 Circuit and Related Components

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To keep the design looking like the original data sheet logic diagram, as published by companies that include NXP Semiconductors and Texas Instruments, a custom “T notS-R FlipFlop” subcomponent and corresponding assembly file was first created. This subcomponent was reused 4 times in the main IC logic diagram. An assembly file called 74hc193.asy was also created. It includes all pins used on the commercial IC except ground and Vcc. The IC’s internal power supply is not simulated by the Linear Technologies’ gates, and so they are not used or required in this design either.

Each gate within the design has a few variables assigned to them so that the IC remains flexible and easy to reuse in new projects:

• tdgate td (propagation time delay assigned to each gate)
• tdgate2 td (propagation time delay assigned to the D FlipFlop)
• tripdtgate tripdt (td’s accuracy band assigned to each gate including the D FlipFlop)
• vhighgate logical high value for each gate and D FlipFlop
• vlowgate logical low value for each gate and D FlipFlop

These variables can be assigned their corresponding time and voltage values using a .param statement placed in the main circuit. These values are then within scope for automatic reuse by the 74HC193 component and flipflop subcomponent simulations. Below is an example of how parameter assignment can be made (as used in the test circuit described next):

.param tdgate=10n tdgate2=3*tdgate tripdtgate=1n vhighgate=5v vlowgate=0v

The Test Circuit

See figure 2 below for a screen shot of the completed simulation test circuit.

Figure 2 – 74HC193 Test Circuit and Truth Table Waveforms

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The test circuit demonstrates the use of the 74HC193 component assembly.

Individual pulse voltages are applied to the component’s input pins to validate the new device:

• (asynchronous master reset) pulsed high at the beginning and end of simulation. Unlike the waveform often shown in the 74xx193 IC’s datasheet sequence diagram (see page 7 of 29 in this version published by NXP), the second reset pulse was added to insure that Q0 to Q3 output values really do reset.
• (asynchronous parallel load) pulsed low near beginning of simulation to set flip-flop outputs (Q0 to Q3) to the data input values (D0 to D3).
• (rising edge triggered count up clock) pulsed low several times to demonstrate both the count up behavior of the flip-flop outputs and the terminal count up, or carry, () output.
• (rising edge triggered count down clock) pulsed low several times to demonstrate both the count down behavior of the flip-flop outputs and the terminal count down, or borrow, () output.
• to (data input pins) tied to either logic-high or logic-low for this simulation. The logic-low is constructed from a zero voltage component instead of simply being tied to the LTspice global circuit common node (ground). This is because of the LTspice gate component’s special behavior in removing the simulation of individual gate pins tied to the common node ground.

All voltage sources are referenced using the same high and low voltages described in the previous section: vhighgate and vlowgate. These values can be reassigned to all gates, all at once, using the .param statement discussed above.

Download the Circuits

The 74HC193 component, subcomponent, assemblies, test circuits, and plot control files can all be downloaded without restriction in their use. The datasheet supplied does have some licensed use restrictions, as defined in its last page. The reference to the 74HC193 data sheet from NXP Semiconductors is in no way an endorsement of the company or its products, but it is the most recent and best documented behavior for this device that I have found.

1. 74hc193.74hct193.pdf 74HC193 data sheet published by NXP Semiconductors in Adobe Acrobat PDF format
2. 74HC193_test.asc test circuit as shown in figure above
3. 74HC193_test.plt plot control file used by the test circuit above
4. 74HC103_test2.asc debug circuit used to debug errors in original design
5. 74HC103_test2.plt plot control file used by the test2 circuit above
6. 74HC193.asc circuit component
7. 74HC193.asy circuit component assembly used in the test circuit above
8. TnotSRFlipFlopFromD.asc circuit subcomponent used by 74HC193.asc file above
9. TnotSRFlipFlopFromD.asy circuit subcomponent used by 74HC193.asc file above
10. The screenshots saved as png files – as shown in this blog post
11. readme.txt text file granting a license to use the 74HC193 simulation files listed above without restriction and without warranty

Download the files listed above for your LTspice designs all in one zipped directory.

Technorati Tags: Ron Fredericks, component, LTspice, SwitcherCAD III, circuit simulation, schematic capture, 74193, IC, circuit, simulation, timing, voltage, CMOS, Schottky, TTL, Linear Technology

Well, I did not find a previous inventor for my IC simulation, but I did get confirmation that the gate build-up was a common strategy. And, this same forum engineer supplied me with a copy of an IC simulation of his own – one very similar to my IC requirement – he supplied a symbol and sample test bed to accelerate my learning curve. Here is a link to my support dialog.

I would like to thank Helmut Sennewald for his time and excellent service to the LTspice yahoo forum. It is his effort and many others who make this forum such a valuable community resource. This forum in turn, has made the LTspice/SwitcherCAD III circuit capture and spice tool a viable design tool for many embedded component users and EE designers.

Introducing the T S-R Flip-Flop

To build my new IC, I had to build a new digital logic block. This component is a Toggle Flip-Flop with Set and Reset functions added. In this blog post I introduce my readers to this new component and share the simulation circuit for others to use and learn from.

See the figure below for an initial design of the T S-R Flip-Flop, including a truth table in the form of a waveform diagram, the circuit, a pulse detector sub-circuit and their related assemblies. This circuit is just an initial design because it uses an S-R Flip-Flop and a simple pulse detector sub-circuit for its clock.

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Final Design for the T S-R Flip-Flop

This section of my post is an update, thanks to a review by Helmut Sennewald. See figure below for my final design of the Toggle S-R Flip-Flop. This design overcomes two problems in my initial design, both resolved by starting with the D Flip-Flop with its built-in clock. The reuse of this more full-featured LT supplied component in my design eliminated the home-brew pulse maker sub-circuit. And in so doing, the slower S-R Flip-Flop. Slower because I had to set the SpiceLine time delay to a minimum of 20 nanoseconds (or td >= 2x the gate time delay) to support the simulation of my simple pulse maker sub-circuit. The D Flip-Flop has an internal clock so I could eliminate the pulse maker sub-circuit. End result: one less sub-circuit and faster Flip-Flop simulation using a time delay set to a minimum of 10 nanoseconds (or td >= 1x the gate time delay).

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Download

To test my knowledge of digital design using the LTspice tool, I created a number of similar flip-flop components which are included in the download:

1. S-R Flip-Flop test circuit
2. S-R Flip-Flop with Enable gate and test circuit
3. S-R Flip-Flop with rising edge clock and test circuit
4. J-K Flip-Flop with rising edge clock and test circuit
5. D Flip-Flop with Enable gate and test circuit
6. T S-R Flip-Flop from S-R Flip-Flop and test circuit (initial design)
7. Rising Edge Pulse Detector (not high performance design)
8. T S-R Flip-Flop from D Flip-Flop and test circuit (final design)

Download the components listed above for your LTspice designs all in one zipped directory.

Technorati Tags: Ron Fredericks, component, circuit, simulation, LTspice, Linear Technologies, Helmut Sennewald, embedded

SwCAD III First Time Use

The tool is free and comes with a lot of support. I downloaded the software and installed it very easily on my Windows XP PC. It includes a graphical schematic design tool with lots of ready made simulated components, including an NE555 for my initial project. Designing the circuit with the built-in CAD tool works very intuitively. While the LTspice simulation took a bit of head scratching before it worked for me.

I was able to configure and run the simulation using the drop down tools menu and the little “running person” icon on the tool bar. But all I could get out of the simulation was a black screen with voltage and timing ticks along the left and bottom edges. So my first problem was in realizing that the visual display would remain black and traceless until I put the mouse cursor over a wire then click. When the little instrument probe showed up as my mouse icon, I realized what was going on here. With the mouse click, waveform tracings would appear in the black panel.

My second problem was that the circuit would not oscillate. Not good for an oscillator design. First, I forgot to connect the 555′s threshold + trigger pins to the R2-C2 node using the wire tool. But still no oscillation, just flat line traces were observed. Now I already know that getting circuits to oscillate follows Murphy’s Laws: Oscillators remain stable, Amplifies and Buffers oscillate, whenever possible. I found a note on the Old School Hacker blog with a fine solution. You must simulate the circuit with a power supply starting from 0 volts rather than just have an instant on Vcc power supply.

In hind sight dah, its the initial transient response from the circuit’s components that kicks the oscillator into oscillating.

After a little practice I improved the schematic diagram with the use of named nodes and seperation of the temporary load resistors R3 and R load from the more permanent circuit components. The load resistors are just place holders for a real load to be added to the circuit schematic next. Look for my next blog post on this subject.

Finally, I used the cursor measurement facility built into the LTspice window (trace window). With this feature, I was able to make “real” measurements on the waveform for frequency and duty cycle.

Circuit

Here is what I was able to generate using the LTspice/SwitcherCAD III tool:

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Download 555 Astable Flip-Flop Schematic Circuit Diagram>

Referring to the figure above:
   Green Trace -> Output (IC 555 pin 3)
   Blue Trace -> Trigger / Threshold (IC 555 pins 2 & 6)
   Red Trace -> Discharge (IC 555 pin 7)

The Astable Multivibrator

The circuit shown above will trigger itself and free run as a multivibrator. The capacitor C₂ charges through resistors R₁ and R₂ yet discharges through R₂ only. Thus, the duty cycle (D) may be precisely set by the ratio of these two resistors. The capacitor charges and discharges between 1/3 Vcc and 2/3 Vcc. But the initial pulse charges C₂ starting from 0 Vcc and so this first pulse duty cycle is unique. Since the charge rate and the threshold levels are directly proportional to the supply voltage Vcc, the frequency of oscillation (f) is independent of the supply voltage.

Frequency Calculation	Duty Cycle Calculation
Measured = 1.8 hertz	Measured = 0.60
Where:      is frequency in hertz      is capacitance in farads      is resistance in ohms	Where:      is duty cycle      is non-zero output duration      is the period of the output      is resistance

Reference

• 555 Datasheet icm7555.pdf
• Linear Technology’s SwitcherCADâ„¢ III Landing Page

Technorati Tags: Ron Fredericks, schematic, LTspice, SwitcherCAD III, simulator, Spice, CAD