Archive for the 'Uncategorized' Category

Dual-Channel Digital Volume Control Circuit Simulation

Wednesday, January 11th, 2012

Ron Fredericks writes: In today’s post, I will demonstrate the value in using LTspice to simulate a complete circuit.

In several previous LTspice posts I described how to use the simulator as a test jig for single IC’s and gates. Each block in a circuit should be tested within LTspice before creating a multi-circuit simulation to verify performance against expected results. The test jig process included downloading a custom gate, IC, and spice code for the cd4066 bi-polar analogue switch from the yahoo LTspice user group, and the creation of my own 74LS193 pre-setable up/down counter from primitive logic gates. Ltspice is very flexible. Most discrete components are readily available in the library, with a great support group from on yahoo. There are a wide variety of spice and pspice models to important from many Internet sources as well..

The Circuit to Simulate

I came across this digital volume control circuit during a web search. The circuit seems to be fairly popular as it shows up in thousands of places on the web. I thought it would be a good place to start my investigation of digital volume control even though there are many industry specific chips out there to manage some of these functions as well as chips that offer much larger feature sets. With this circuit I hope to expand on the features to create new volume control and measurement circuits – perhaps while investigating the value in using an more advanced volume control chip.

This circuit could be used for replacing your manual volume control in a stereo amplifier. In this circuit, push-to-on switch S1 controls the forward (volume increase) operation of both channels while a similar switch S2 controls reverse (volume decrease) operation of both channels.
Here IC1 timer 555 is configured as an astable flip-flop to provide low-frequency pulses to up/down clock input pins of pre-setable up/down counter 74LS193 (IC2) via push-to-on switches S1 and S2. To vary the pulse width of pulses from IC1, one may replace timing resistor R1 with a variable resistor.

Operation of switch S1 (up) causes the binary output to increment while operation of S2 (down) causes the binary output to decrement. The maximum count being 15 (all outputs logic 1) and minimum count being 0 (all outputs logic 0), it results in maximum and minimum volume respectively.

The active high outputs A, B, C and D of the counter are used for controlling two quad bi-polar analogue switches in each of the two CD4066 ICs (IC3 and IC4). Each of the output bits, when high, short a part of the resistor network comprising series resistors R6 through R9 for one channel and R10 through R13 for the other channel, and thereby control the output of the audio signals being fed to the inputs of stereo amplifier. Push-to-on switch S3 is used for resetting the output of counter to 0000, and thereby turning the volume of both channels to the minimum level. — Sheena K. for electronicsforu magazine

Dual-Channel Digital Volume Control Circuit (click to enlarge)

The LTspice Simulation

The Circuit

Volume Controller Schematic in LTspice (click to enlarge)

The Simulation Results

LTspice Simulation Results (click to enlarge)

Simulating the CD4066 Quad Bilateral Switch With LTspice

Monday, December 12th, 2011

Ron Fredericks writes: Today is Robert Norton Noyce’s birthday (born 12/12/1927) – co-inventor of the integrated circuit (IC). So I thought I would take a few minutes and document my work modeling the CD4066 quad bilateral switch with the LTspice simulator.

In this post I describe how flexible LTspice can be as a general SPICE circuit simulator, and how accurate its behavior can be in comparing LTspice test results with the physical IC’s datasheet. In this example I use the CD4066B as the IC to model. I test the model using its characteristic “on” resistance curves under various voltage and current operating conditions. I conclude by using a standard CD4066 datasheet to verify the accuracy of the model.

Meanwhile this is the last IC I need to simulate the analog section of the digital volume control circuit using LTspice I mentioned in two of my previous blog entries:

Define one of four bilateral switches on CD4066 for LTspice


To get the CD4066 IC into my circuit simulation, I first created a symbol for one of the four bilateral switches in this package, and defined a SPICE subcircuit definition for the switch using existing SPICE CD4007 gate models as the starting point.

Symbol for one of four bilateral switches on the CD4066 IC


LTspice symbol for one of four bilateral switches on cd4066 (click to enlarge)

LTspice Subcircuit Definition for CD4066
Note the LTspice implementation of the SPICE language is highlighted (below) using my own GeSHi language highlighter library with key sections of the language (.model and .subcircuit) hyper-linked into SPICE language definitions that I have created on the contributor pages of this website. SPICE is a difficult language to highlight using GeSHi because many of the SPICE language constructs are so short that they overlap with longer language constructs. I plan to add more language definitions in the future as my circuit models need them, and I continue to find unique look-up algorithms to match GeSHi language highlighter categories.


  2. * CD4066 Analog Switch
  3. * SYM=CD4066
  4. * Transistor models are from LTspice group member kcin_melnick
  5. * See message number 16897,
  6. * Analog Switch Control In Out Vdd Vss
  7. .SUBCKT CD4066 2 11 4 10 7
  8. X1 2 6 10 7 INVERT
  9. X2 6 1 10 7 INVERT
  10. M1 14 6 7 7 CD4007N
  11. M7 11 6 14 10 CD4007P
  12. M3 11 1 14 14 CD4007N
  13. M4 11 1 4 14 CD4007N
  14. M8 11 6 4 10 CD4007P
  15. .SUBCKT INVERT 1 2 3 4
  16. * Inverter In Out Vcc Vss
  17. M1 2 1 3 3 CD4007P
  18. M2 2 1 4 4 CD4007N
  19. .ENDS
  20. .MODEL CD4007N NMOS (
  21. + LEVEL=1 VTO=1.44 KP=320u L=10u W=30u GAMMA=0 PHI=.6 LAMBDA=10m
  22. + RD=23.2 RS=90.1 IS=16.64p CBD=2.0p CBS=2.0p CGSO=0.1p CGDO=0.1p
  23. + PB=.8 TOX=1200n)
  25. .MODEL CD4007P PMOS (
  26. + LEVEL=1 VTO=-1.2 KP=110u L=10U W=60U GAMMA=0 PHI=.6 LAMBDA=40m
  27. + RD=21.2 RS=62.2 IS=16.64P CBD=4.0P CBS=4.0P CGSO=0.2P CGDO=0.2P
  28. + PB=.8 TOX=1200N)
  29. .ENDS

Testing the CD4066 Circuit in LTspice

Finally, I dragged the symbol with subcircuit models into my LTspice program and ran a series of tests to demonstrate the “on” resistance characteristics associated with the switch at various voltage and current values. Note the multicolored graph showing the resistance curves at various VI levels.


VI curves and circuit schematic for cd4066 bilateral switch under test (click to enlarge)

Get these files from LTspice Yahoo Group

The 4 main files used to create this demo circuit can be obtained from LTspice Yahoo Group. Special thanks to Helmut Sennewald

See the figure below…

LTspice Yahoo Group File List (click to enlarge)

Comparison of LTspice circuit simulation with datasheet

The TI datasheet compares favorably with my simulations. The LTspice “on” resistance curves and values are nearly exactly the same as those shown in figures 2,3, and 4 of TI’s datasheet (page 6) for the range I tested.

At this stage of development in simulating the analog path for my automatic volume control circuit, I see that the “on” resistance curve may create an unstable signal path under normal audio conditions unless the operating voltage (Vcc ) is much higher than the original circuit’s proposed 5 VDC power supply.


Linear Technologies LTspice Landing Page

Texas Instruments datasheet for the CD4066B

What’s All This CD4007 Stuff, Anyhow?
Bob Pease | ED Online ID #6073 | April 5, 1999

Fault in CD4066 Model
kcin_melnick | LTspice Yahoo Tech Group Message #16897 | June 24, 2007

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Forum Newsletter – New RTOS Videos

Monday, December 5th, 2011

Embedded Components and Tools forum: December 2011

The forum introduces real-time embedded systems technology designed, reviewed, or filmed by Ron Fredericks. Ron focuses on hardware, software, and cloud services for the embedded systems industry through the platform and his Bay Area media lab located in Sunnyvale California called LectureMaker LLC.


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How to Use LectureMaker Video Studio for Hardware/Software Demos

Tuesday, March 23rd, 2010

Ron Fredericks writes: Have you tried to post software demo’s on youtube? If so, then this online video produced from LectureMaker’s high-tech video studio can help you get up to speed very quickly on how to solve the video publishing problems associated with software screencasting. The video demonstrates how to build a simple external hard disk starting from an enclosure for USB and eSTATA connectivity with a PC, MAC, or Linux box. The video concludes with a walk-through on how to format the disk into two partitions.


Hardware Software Demonstration
Presented by Ron Fredericks, Business Videographer and Open Studio Director

Video Link

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Embedded Hypervisor – the RTOS in the clouds

Thursday, February 11th, 2010

Ron Fredericks writes: I just read the press release on Wind River’s Hypervisor and Mark Hermeling’s blog on the subject of multi-core virtualization.

Wind River gets a second chance on connecting smart devices into the enterprise world.

One of their previous attempts was Wind’s office political initiative into Embedded BSD/OS. I thought the BSD OS play was great for Wind River if only they connected their robust multi-core OS from the smart device into the enterpise. Now I see and hope that Wind River has learned from this prior effort and is off to a second chance.

The classic Hypervisor diagram
The Wind River Hypervisor

So there are a few different kinds of hypervisor: here is a link to a short discription of the server OS, versus their type 1 and 2 hypervisors. Follow Wind River to learn more about their vision for an embedded system hypervisor.

Now of course the cloud is more tied to the embedded system world than ever. Just look at UC Berkeley’s upcoming annual technology day called BEARS, where CAL’s EE and CS researchers share with the technology industry.

I sure hope Wind River will be attending!

This year’s 2010 Berkeley EECS Annual Research Symposium event is called: From Clouds to Sensors – A Berkeley View

BEARS symposium image: from clouds to sensors
The CAL BEARS 2010 Symposium view from the clouds

Ron has been in the enterprise, embedded systems, and smartphone technical marketing and partner development for the past 15+ years. Contact him to learn more about how relationship marketing can be used to connect the embedded systems hypervisor to the enterprise clouds with effecient use of industry and university partnerships.

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Bay Area R User Group 2009 Kickoff Video

Thursday, April 2nd, 2009

Ron Fredericks writes: In February I attended the Bay Area R User Group meeting held at Predictive Analytics World 2009. Michael E. Driscoll, one of the meeting co-chairs, was gracious enough to let me capture the video as a “light house” project for


  • Bo Cowgill, Google
  • Itamar Rosenn, Facebook
  • David Smith, REvolution Computing
  • Jim Porzak, The Generations Network


  • Michael E. Driscoll, Dataspora LLC
The R and Science of Predictive Analytics:
Four Case Studies in R
Learn more and watch lecture

Watch this video to learn about:

  1. The open-source analytics programming language called R
  2. How Google and Facebook approach analytics to predict their web user community’s behavior
  3. Where to download R and get enterprise level support
  4. How the meeting co-chairs use R

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The Marketing Bubble

Thursday, October 9th, 2008

The marketing bubble’s effect on embedded device software developers


Ron Fredericks writes: In yesterday’s marketing webinar: Beyond Monitoring: Managing Social Media Engagement by SocialRep‘s CEO, Chris Kenton, viewers were riveted by his inside knowledge on social media’s word-of-mouth marketing. Chris is well known for his combination of social media marketing knowledge as well as his ability to strip away the facts from the hype.

To set the stage, my own readers have found my marketing FAQ to be a very popular read for the embedded device software industry: Assessing marketing’s critical role in organizational performance. Read on to see if it will blend!


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How to Leverage the Value of a Board Support Package

Wednesday, November 21st, 2007

Ron Fredericks writes: There are three separate views to what defines an effective Board Support Package (BSP). I believe each of these views is correct as independent descriptions of a BSP. But together these views provide insight into the embedded target from equally important perspectives or engineering disciplines. Read this post to learn more about the essence of embedded systems and how Wind River’s VxWorks BSP architecture has been a critical success factor in comparison to many other real-time embedded operating system executives and kernels available today.

I chose to discuss Wind River’s VxWorks BSP because of my familiarity with their product line, my understanding of their BSP as a competitive product compared to other real-time kernels, and because of my industry accomplishments working with Wind River’s BSPs:

  • Ron Fredericks wins Wind River’s prestigious Navigation Award for designing, launching, and marketing the first online interactive social network for BSP’s. more>
  • Ron Fredericks wins Aiysis’ Million Dollar Club Award for nurturing a Wind River partnership between VxWorks and Aiysis DriveWay BSP tool kit that generated over one million in annual sales. more>
  • Ron Fredericks co-author’s an article with Xilinx on How to Design Field Upgradable Systems based on FPGA Internet connectivity with VxWorks BSP’s. more>
  • Ron Fredericks produces an online video: How to Prototype a Device Driver [or BSP] in Less Than – Wow! – 5 Minutes for a Freescale application processor / communications co-processor System on Chip (SoC). more>

A similar high level discussion can not be made for most embedded Windows or embedded Linux BSP’s today. This is because the BSP for these monolithic kernels are not as modular as a real-time executive kernel such as VxWorks. Indeed other real-time kernel vendors can and do take advantage of the BSP too. But, the VxWorks BSP just took more advantage of this natural separation between board support and kernel tasks earlier in the marketplace and has been an advantage for its customers as a result ever since.

Target Board with BSP connected to a host workstation
Figure 1 – Embedded device with BSP connected to a host workstation

As shown in Figure 1, most BSP’s today, even those for embedded Windows and embedded Linux, do have a robust set of boot options. In many cases a BSP can be used on its own to network attach to a shared file system where the full operating system and application can be loaded. In this way, a device under development need not be the device where development takes place. The BSP in this case forms the basis for a cross-platform development environment – a big plus for developers of embedded systems. Developers often expect cross-platform development to include a BSP with a limited network stack to load new code onto the target hardware during a cold reset. The BSP might use JTAG on-chip run-time control, RS232 serial port, FTP, Bootp, TFTP and RARP, or even a command shell with a full network stack, as the boot loading protocol. But what ever host to target connectivity is used, cross-development allows a high end workstation to be used for time-saving development along with an easy way to download the resulting compiled relocatable object code or a linked and located image onto an embedded target.

For hardware vendors, the BSP is a very useful partner tool. If a hardware vendor makes a set of boards along with a bus pre-assembled as a subsystem or just a single board computer, the BSP allows its clients to leverage this hardware for software development right away. So a hardware vendor can select major operating systems that meet the needs of its target client base and offer a BSP suitable for these operating systems. Usually the BSP is not a licensed product from the operating system vendor and can be bundled royalty free or under very libral license fee conditions. In this way, the operating system vendor or the open-source community, can partner with this hardware platform as a known reference for direct end products or for development of custom products. The horrible alternative is a slow hardware bring-up using new hardware for the first time to build a unique BSP – a very slow and expensive procedure where few software debug tools are available. JTAG or other N-wire run-control devices can be used with an operating system vendor’s debugger in some cases when a robust BSP is not already available. Silicon vendors and I/O device vendors can leverage this technical marketing strategy too.

I encourage Microsoft and embedded Linux communities to consider improving their BSP strategy to deliver more value from a separate BSP structure too. I also encourage my readers to go ahead and submit comments to this blog post if you know of other vendors with good BSP designs as the marketplace is always changing.


How to build Dean Lee’s Syntax Highlighter from latest components

Tuesday, May 29th, 2007

Ron Fredericks writes: In my last two posts:

During my research to solve the word wrap problem, I discovered a few more issues leading me to update Dean’s plugin with the latest version of GeSHI (an open-source project: Generic Syntax Highlighter for php. Highlight many languages, including PHP, CSS, HTML, SQL, Java, Assembler, and C for XHTML compliant output) and removal of unused files. I thought other WordPress bloggers might like to take advantage of the latest code too, so I document the steps needed to build a clean plugin with the latest components.

Flow Chart / Swim Lanes Widget
Below is a Flash widget I built to document the steps needed so you can roll your own up-to-date plugin. Follow these steps and you won’t have to be a programmer to get the benefits from the latest versions of these program components. The widget actively links to the latest PHP files and CSS classes:


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How to Fix Dean Lee’s Source Code Highlight Plugin

Sunday, May 27th, 2007

Ron Fredericks writes: In my previous post, I discuss Dean Lee’s source code syntax highlighting plugin for WordPress. It delivers all the great features of the GeSHi open-source highlight project for Wordress bloggers.

Yet some source code displayed badly – turning a developer’s nice clean style into a chaotic and messy format. I demonstrated the display problem using a perl sendmail script I plan to discuss in a future blog post. The problem had to do with some kind of whitespace word wrap issue.

I tested various features of CSS and DIV tag attributes created by Dean’s plugin and the GeSHi php code. I am happy to say, I found a simple one-line solution. My solution is in updating Dean’s CSS container class to force white space not to wrap.

Here is my solution:
Add this property to Dean’s “ch_code_container” CSS class:

white-space: nowrap;


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