The marketing bubble’s effect on embedded device software developers

Introduction

Ron Fredericks writes: In yesterday’s marketing webinar: Beyond Monitoring: Managing Social Media Engagement by SocialRep’s CEO, Chris Kenton, viewers were riveted by his inside knowledge on social media’s word-of-mouth marketing. Chris is well known for his combination of social media marketing knowledge as well as his ability to strip away the facts from the hype. To set the stage, my own readers have found my marketing FAQ to be a very popular read for the embedded device software industry: Assessing marketing’s critical role in organizational performance. Read on to see if it will blend!

The Marking Bubble Defined

Chris introduced us to the “marketing bubble”, a marketing event in progress now. Chris may be the first to realize and share the underlying problem so clearly. Marketing has always been a word-of-mouth vehicle since the beginning of human conversations - we’re just not old enough to know it! Check out the Word Of Mouth Marketing Association’s definition of word of mouth marketing. Chris made the case that professional marketers’ tools over the past 130 years have managed to bypass the value of word of mouth by blasting their messages into public and commercial communities to literally overpower the word-of-mouth model using Print, Radio, TV, Mass Markets, and the Internet. Yet the marketing bubble is now bursting as the Internet continues to host an exploding number of social media tools: - tools that extend word of mouth conversation through online social media platforms, popular content management sites, and even a new form of in-person meet up tool that can quickly assemble like-minded individuals into localized events.

Here is a short list of some of the more common word-of-mouth social media platforms that can be leveraged as microsites:

• LinkedIn: A how-to example
• Squidoo: A how-to example
• Facebook: A how-to example
• YouTube: A how-to example [will it blend]
• Ning: A how-to example
• Twitter: A how-to example
• Meetup: A how-to example

These platforms are also some of the leading causes for the marketing bubble. Check out http://www.alexa.com for further research into tools that specialize by industry and/or region.

These microsites often include application programmable interfaces (API’s), news feeds, user profiles, links to friends, groups, photos/videos, chat, and their own markup languages to build relationships and quickly share short conversations. These features are a little different than the more traditional social media platforms such as blogs, forums, wikis, chat, and idea managers.

Word-of-Mouth Customer Relationship Lifecycle

Chris presents an integrated marketing plan that starts with several forms of monitoring to measure influential conversations followed by use of a wide selection of social media tools.

Monitoring Social Networks: Metrics

Monitoring social media activity is one of the basic requirements to managing social media engagements. A company starting up with a social media marketing program nearly always intends to find and engage with their most influential online customers. But Chris goes on to point out that companies often fail in their use of social media marketing tools. The problem boils down to the fine art of adapting to the trends their team discovers after their initial engagements with social media. I call this the company’s analytics culture. There are thee areas that a company can monitor:

• Media: The web pages and web sites that customers use or visit [commonly monitored]
• Technology: The technology behind a company’s products [often ignored], and
• Finance: The financial goals surrounding a company’s sales activity [often ignored].

The problem stems from a company’s tendency to focus too much on web page tools that monitor media, and in so doing, fails to develop an adaptable action plan that includes the other two key domains of marketing operations: technology and finance. After Chris pointed this out in his webinar, it seems very clear to me that a company needs more than trends in page clicks or page visitors to build the business case for change within a company’s executive team decision-makers. Two solutions that have become popular by social marketers in bridging the gap between initial engagement, and adapting their business activities towards the needs of the community, are in the reuse of these two popular tools already in use by most companies:

• Integration of the company’s Goggle AdWords data, and the
• Integration of the company’s CRM – SalesForce.com in particular.

Using Monitored Results: Analytics

Chris and others point out that although the use of CRM tools are well intentioned – a large percentage of marketers do not get the needed monitoring data to successfully adapt to changes or to meet the changing needs within the company’s community. Chris describes how a company can use their CRM as part of an integrated analytics strategy:

• Use reports and analytics stored within the CRM
• Integration of a word-of-mouth program integrated with the CRM
• Creation of an advisory board from the most influential customers identified from CRM

Building a Program

Chris then presented a Word-of-Mouth program built around a Customer Relationship Lifecycle. He goes over some details, shows some steps to be taken, and highlights a case study. I summarize his program from a B2C perspective here:

1. Awareness:
   • Value: Branding
   • Tools: Web ads, Search engine optimization or marketing, Viral video, Targeted community sponsorship
   • Marketing framework: Conversation + Content
2. Knowledge:
   • Value: Branding and Marketing
   • Tools: Landing pages, Microsites, and Webinars
   • Marketing framework: Conversation + Content + Community
3. Consideration:
   • Value: Branding, Marketing, and Sales
   • Tools: Reviews & comparisons, Hosted chat, and Webinars
   • Marketing framework: Conversation + Content + Community
4. Selection (or when a customer takes the desired action like buys the product):
   • Value: Branding, Marketing, and Sales
   • Tools: Online discount offers, and Hosted chat
   • Marketing framework: Conversation + Content + Community + Customer advisory council
5. Satisfaction:
   • Value: Branding, Marketing, and Sales
   • Tools: Surveys, Support forum, Support chat, and Customer communities
   • Marketing framework: Conversation + Content + Community + Customer advisory council
6. Advocacy:
   • Value: Branding and Marketing
   • Tools: Referral offers, Peer forums, Product networks, and Consumer communities
   • Marketing framework: Conversation + Content + Community + Customer advisory council
7. Loyalty:
   • Value: Branding
   • Tools: Discounts, Insider forums, Product networks, and Customer communities
   • Marketing framework: Conversation + Content + Community + Customer advisory council

Some steps along the way in the execution of a word-of-mouth customer relationship lifecycle program:

• Engage in useful conversations:
  • Targeted monitoring and metrics,
  • Managed engagement,
  • Trend tracking,
  • Media, pundit, and influencer profiling.
• Create a cross-functional Social Media A-Team:

• Marketing,
• PR,
• Product marketing,
• Sales,
• Customer service,
• Engineering, and
• Legal.

Some Final Thoughts For Embedded Device Software Developers

Most of what I summarize above is focused on B2C relationships and comes out of my review of Chris Kenton’s great webinar: Beyond Monitoring: Managing Social Media Engagement. Of course I added my own knowledge and some additional references to help my readers get a fast overview of the landscape.

Building a social media marketing program would have some differences when it comes to software developers focused on embedded devices including:

• A smaller volume of activity
• A scarcity of good marketers and public communicators with a working knowledge of the deeply technical subject matter and its assocated value chain
• A larger barrier between the engineers who make and use software:
  • Those that build the software tools targeting a wide variety of programmers, engineers, and architects,
  • Those that create the run-time device optimized software platforms targeting embedded software engineers, and
  • Those that build the differentiating applications targeting the end user.
• A different marketing framework focused on the collective business and not the individual:
  • See Four Steps to Creating a Gorilla Partnership for some insight on building business-to-business frameworks
  • Perhaps the framework will have unique features for open-source vs. OEM software license models
• Look for social media marketing tools that integrate with software developer frameworks, perhaps as plugins
  • Basic collaboration for developers looks like code check-in and check-out for global teams, not like a tweet.
  • Maybe the next tweet will be a twitter plugin that adds another Eclipse perspective, for example.

Yet there can be no doubt that the short word-of-mouth conversations on microsites will burst the marketing bubble. This would be true for any marketer planning there next engagement, for businesses focused on building software for embedded devices, or for the device manufacturer trying to leverage software developers. Chris Kenton’s marketing webinar: Beyond Monitoring: Managing Social Media Engagement is a good place to start building a word-of-mouth marketing plan. His offering demonstrates the most integrated set of tools I’ve seen - to build a substantial word-of-mouth marketing program.

Thanks to Chis for making it very clear that social media word-of-mouth marketing is not a program to be considered independently of other marketing activities. Instead it’s just a mater of time before the bubble bursts in your market sector. The real question is more of when, than if, a company should add word-of-mouth social media tools to their integrated marketing strategy.

Technorati Tags: marketing bubble, software developer, Ron Fredericks, SocialRep, Chris Kenton, social media, marketing, embedded device, software, word-of-mouth, Print, Radio, TV, Mass Markets, Internet, social media, LinkedIn, Squidoo, Facebook, YouTube, Ning, Twitter, Meetup, microsites, blogs, forums, wikis, chat, idea managers, Customer Relationship Lifecycle, conversations, analytics, Media, Technology, Finance, Goggle, AdWords, CRM, SalesForce.com, Awareness, Knowledge, Consideration, Selection, Satisfaction, Advocacy, Loyalty, Social Media A-Team, Marketing Engineer, collaboration

My WordPress blog on this site is well protected thanks to Akismet. They also have a Drupal project too: drupal.org/project/akismet

You can follow my Drupal site blog - as a work in progress - from here:
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All circuits related to this 74HC193 simulation are available here>

The 74HC193 Component

See figure 1 below for a screen shot of the completed design. The circuit was built from the digital gates in the component library supplied with the original Linear Technology’s free LTspice tool.

Figure 1 - 74HC193 Circuit and Related Components

View larger image>

To keep the design looking like the original data sheet logic diagram, as published by companies that include NXP Semiconductors and Texas Instruments, a custom “T notS-R FlipFlop” subcomponent and corresponding assembly file was first created. This subcomponent was reused 4 times in the main IC logic diagram. An assembly file called 74hc193.asy was also created. It includes all pins used on the commercial IC except ground and Vcc. The IC’s internal power supply is not simulated by the Linear Technologies’ gates, and so they are not used or required in this design either.

Each gate within the design has a few variables assigned to them so that the IC remains flexible and easy to reuse in new projects:

• tdgate td (propagation time delay assigned to each gate)
• tdgate2 td (propagation time delay assigned to the D FlipFlop)
• tripdtgate tripdt (td’s accuracy band assigned to each gate including the D FlipFlop)
• vhighgate logical high value for each gate and D FlipFlop
• vlowgate logical low value for each gate and D FlipFlop

These variables can be assigned their corresponding time and voltage values using a .param statement placed in the main circuit. These values are then within scope for automatic reuse by the 74HC193 component and flipflop subcomponent simulations. Below is an example of how parameter assignment can be made (as used in the test circuit described next):

.param tdgate=10n tdgate2=3*tdgate tripdtgate=1n vhighgate=5v vlowgate=0v

The Test Circuit

See figure 2 below for a screen shot of the completed simulation test circuit.

Figure 2 - 74HC193 Test Circuit and Truth Table Waveforms

View larger image>

The test circuit demonstrates the use of the 74HC193 component assembly.

Individual pulse voltages are applied to the component’s input pins to validate the new device:

• (asynchronous master reset) pulsed high at the beginning and end of simulation. Unlike the waveform often shown in the 74xx193 IC’s datasheet sequence diagram (see page 7 of 29 in this version published by NXP), the second reset pulse was added to insure that Q0 to Q3 output values really do reset.
• (asynchronous parallel load) pulsed low near beginning of simulation to set flip-flop outputs (Q0 to Q3) to the data input values (D0 to D3).
• (rising edge triggered count up clock) pulsed low several times to demonstrate both the count up behavior of the flip-flop outputs and the terminal count up, or carry, () output.
• (rising edge triggered count down clock) pulsed low several times to demonstrate both the count down behavior of the flip-flop outputs and the terminal count down, or borrow, () output.
• to (data input pins) tied to either logic-high or logic-low for this simulation. The logic-low is constructed from a zero voltage component instead of simply being tied to the LTspice global circuit common node (ground). This is because of the LTspice gate component’s special behavior in removing the simulation of individual gate pins tied to the common node ground.

All voltage sources are referenced using the same high and low voltages described in the previous section: vhighgate and vlowgate. These values can be reassigned to all gates, all at once, using the .param statement discussed above.

Download the Circuits

The 74HC193 component, subcomponent, assemblies, test circuits, and plot control files can all be downloaded without restriction in their use. The datasheet supplied does have some licensed use restrictions, as defined in its last page. The reference to the 74HC193 data sheet from NXP Semiconductors is in no way an endorsement of the company or its products, but it is the most recent and best documented behavior for this device that I have found.

1. 74hc193.74hct193.pdf 74HC193 data sheet published by NXP Semiconductors in Adobe Acrobat PDF format
2. 74HC193_test.asc test circuit as shown in figure above
3. 74HC193_test.plt plot control file used by the test circuit above
4. 74HC103_test2.asc debug circuit used to debug errors in original design
5. 74HC103_test2.plt plot control file used by the test2 circuit above
6. 74HC193.asc circuit component
7. 74HC193.asy circuit component assembly used in the test circuit above
8. TnotSRFlipFlopFromD.asc circuit subcomponent used by 74HC193.asc file above
9. TnotSRFlipFlopFromD.asy circuit subcomponent used by 74HC193.asc file above
10. The screenshots saved as png files - as shown in this blog post
11. readme.txt text file granting a license to use the 74HC193 simulation files listed above without restriction and without warranty

Download the files listed above for your LTspice designs all in one zipped directory.

Technorati Tags: Ron Fredericks, component, LTspice, SwitcherCAD III, circuit simulation, schematic capture, 74193, IC, circuit, simulation, timing, voltage, CMOS, Schottky, TTL, Linear Technology

Well, I did not find a previous inventor for my IC simulation, but I did get confirmation that the gate build-up was a common strategy. And, this same forum engineer supplied me with a copy of an IC simulation of his own - one very similar to my IC requirement - he supplied a symbol and sample test bed to accelerate my learning curve. Here is a link to my support dialog.

I would like to thank Helmut Sennewald for his time and excellent service to the LTspice yahoo forum. It is his effort and many others who make this forum such a valuable community resource. This forum in turn, has made the LTspice/SwitcherCAD III circuit capture and spice tool a viable design tool for many embedded component users and EE designers.

Introducing the T S-R Flip-Flop

To build my new IC, I had to build a new digital logic block. This component is a Toggle Flip-Flop with Set and Reset functions added. In this blog post I introduce my readers to this new component and share the simulation circuit for others to use and learn from.

See the figure below for an initial design of the T S-R Flip-Flop, including a truth table in the form of a waveform diagram, the circuit, a pulse detector sub-circuit and their related assemblies. This circuit is just an initial design because it uses an S-R Flip-Flop and a simple pulse detector sub-circuit for its clock.

View larger image>

Final Design for the T S-R Flip-Flop

This section of my post is an update, thanks to a review by Helmut Sennewald. See figure below for my final design of the Toggle S-R Flip-Flop. This design overcomes two problems in my initial design, both resolved by starting with the D Flip-Flop with its built-in clock. The reuse of this more full-featured LT supplied component in my design eliminated the home-brew pulse maker sub-circuit. And in so doing, the slower S-R Flip-Flop. Slower because I had to set the SpiceLine time delay to a minimum of 20 nanoseconds (or td >= 2x the gate time delay) to support the simulation of my simple pulse maker sub-circuit. The D Flip-Flop has an internal clock so I could eliminate the pulse maker sub-circuit. End result: one less sub-circuit and faster Flip-Flop simulation using a time delay set to a minimum of 10 nanoseconds (or td >= 1x the gate time delay).

View larger image>

Download

To test my knowledge of digital design using the LTspice tool, I created a number of similar flip-flop components which are included in the download:

1. S-R Flip-Flop test circuit
2. S-R Flip-Flop with Enable gate and test circuit
3. S-R Flip-Flop with rising edge clock and test circuit
4. J-K Flip-Flop with rising edge clock and test circuit
5. D Flip-Flop with Enable gate and test circuit
6. T S-R Flip-Flop from S-R Flip-Flop and test circuit (initial design)
7. Rising Edge Pulse Detector (not high performance design)
8. T S-R Flip-Flop from D Flip-Flop and test circuit (final design)

Download the components listed above for your LTspice designs all in one zipped directory.

Technorati Tags: Ron Fredericks, component, circuit, simulation, LTspice, Linear Technologies, Helmut Sennewald, embedded

SwCAD III First Time Use

The tool is free and comes with a lot of support. I downloaded the software and installed it very easily on my Windows XP PC. It includes a graphical schematic design tool with lots of ready made simulated components, including an NE555 for my initial project. Designing the circuit with the built-in CAD tool works very intuitively. While the LTspice simulation took a bit of head scratching before it worked for me.

I was able to configure and run the simulation using the drop down tools menu and the little “running person” icon on the tool bar. But all I could get out of the simulation was a black screen with voltage and timing ticks along the left and bottom edges. So my first problem was in realizing that the visual display would remain black and traceless until I put the mouse cursor over a wire then click. When the little instrument probe showed up as my mouse icon, I realized what was going on here. With the mouse click, waveform tracings would appear in the black panel.

My second problem was that the circuit would not oscillate. Not good for an oscillator design. First, I forgot to connect the 555’s threshold + trigger pins to the R2-C2 node using the wire tool. But still no oscillation, just flat line traces were observed. Now I already know that getting circuits to oscillate follows Murphy’s Laws: Oscillators remain stable, Amplifies and Buffers oscillate, whenever possible. I found a note on the Old School Hacker blog with a fine solution. You must simulate the circuit with a power supply starting from 0 volts rather than just have an instant on Vcc power supply.

In hind sight dah, its the initial transient response from the circuit’s components that kicks the oscillator into oscillating.

After a little practice I improved the schematic diagram with the use of named nodes and seperation of the temporary load resistors R3 and R load from the more permanent circuit components. The load resistors are just place holders for a real load to be added to the circuit schematic next. Look for my next blog post on this subject.

Finally, I used the cursor measurement facility built into the LTspice window (trace window). With this feature, I was able to make “real” measurements on the waveform for frequency and duty cycle.

Circuit

Here is what I was able to generate using the LTspice/SwitcherCAD III tool:

View larger image>
Download 555 Astable Flip-Flop Schematic Circuit Diagram>

Referring to the figure above:
   Green Trace -> Output (IC 555 pin 3)
   Blue Trace -> Trigger / Threshold (IC 555 pins 2 & 6)
   Red Trace -> Discharge (IC 555 pin 7)

The Astable Multivibrator

The circuit shown above will trigger itself and free run as a multivibrator. The capacitor C₂ charges through resistors R₁ and R₂ yet discharges through R₂ only. Thus, the duty cycle (D) may be precisely set by the ratio of these two resistors. The capacitor charges and discharges between 1/3 Vcc and 2/3 Vcc. But the initial pulse charges C₂ starting from 0 Vcc and so this first pulse duty cycle is unique. Since the charge rate and the threshold levels are directly proportional to the supply voltage Vcc, the frequency of oscillation (f) is independent of the supply voltage.

Frequency Calculation	Duty Cycle Calculation
Measured = 1.8 hertz	Measured = 0.60
Where:      is frequency in hertz      is capacitance in farads      is resistance in ohms	Where:      is duty cycle      is non-zero output duration      is the period of the output      is resistance

Reference

• 555 Datasheet icm7555.pdf
• Linear Technology’s SwitcherCADâ„¢ III Landing Page

Technorati Tags: Ron Fredericks, schematic, LTspice, SwitcherCAD III, simulator, Spice, CAD

WordPress Math Publisher plugin home page
www.embeddedcomponents.com/blogs/wordpress/wpmathpub/

Usage

An example of how it can be used is your blog posts:

Results in:

where:
is defined as a
is defined as b

References:
  Pascal Brachet’s phpmathpublisher
    Home: www.xm1math.net/phpmathpublisher/
    Usage: www.xm1math.net/phpmathpublisher/doc/help.html
  Matteo Bertini’s WordPress plugin called PHP Math Publisher
    www.slug.it/naufraghi/programmazione-web/wpmathpublisher
  Randy Morrow’s WordPress plugin called Axiom
    wordpress.org/extend/plugins/axiom/#post-2794

Technorati Tags: Ron Fredericks, Embedded Components, WP Math Pub, wpmathpub, math, mathematics, publish, plugin, phpmathpublisher, axiom, MathML, LaTeX

I chose to discuss Wind River’s VxWorks BSP because of my familiarity with their product line, my understanding of their BSP as a competitive product compared to other real-time kernels, and because of my industry accomplishments working with Wind River’s BSPs:

• Ron Fredericks wins Wind River’s prestigious Navigation Award for designing, launching, and marketing the first online interactive social network for BSP’s. more>
• Ron Fredericks wins Aiysis’ Million Dollar Club Award for nurturing a Wind River partnership between VxWorks and Aiysis DriveWay BSP tool kit that generated over one million in annual sales. more>
• Ron Fredericks co-author’s an article with Xilinx on How to Design Field Upgradable Systems based on FPGA Internet connectivity with VxWorks BSP’s. more>
• Ron Fredericks produces an online video: How to Prototype a Device Driver [or BSP] in Less Than - Wow! - 5 Minutes for a Freescale application processor / communications co-processor System on Chip (SoC). more>

A similar high level discussion can not be made for most embedded Windows or embedded Linux BSP’s today. This is because the BSP for these monolithic kernels are not as modular as a real-time executive kernel such as VxWorks. Indeed other real-time kernel vendors can and do take advantage of the BSP too. But, the VxWorks BSP just took more advantage of this natural separation between board support and kernel tasks earlier in the marketplace and has been an advantage for its customers as a result ever since.

Figure 1 - Embedded device with BSP connected to a host workstation

As shown in Figure 1, most BSP’s today, even those for embedded Windows and embedded Linux, do have a robust set of boot options. In many cases a BSP can be used on its own to network attach to a shared file system where the full operating system and application can be loaded. In this way, a device under development need not be the device where development takes place. The BSP in this case forms the basis for a cross-platform development environment - a big plus for developers of embedded systems. Developers often expect cross-platform development to include a BSP with a limited network stack to load new code onto the target hardware during a cold reset. The BSP might use JTAG on-chip run-time control, RS232 serial port, FTP, Bootp, TFTP and RARP, or even a command shell with a full network stack, as the boot loading protocol. But what ever host to target connectivity is used, cross-development allows a high end workstation to be used for time-saving development along with an easy way to download the resulting compiled relocatable object code or a linked and located image onto an embedded target.

For hardware vendors, the BSP is a very useful partner tool. If a hardware vendor makes a set of boards along with a bus pre-assembled as a subsystem or just a single board computer, the BSP allows its clients to leverage this hardware for software development right away. So a hardware vendor can select major operating systems that meet the needs of its target client base and offer a BSP suitable for these operating systems. Usually the BSP is not a licensed product from the operating system vendor and can be bundled royalty free or under very libral license fee conditions. In this way, the operating system vendor or the open-source community, can partner with this hardware platform as a known reference for direct end products or for development of custom products. The horrible alternative is a slow hardware bring-up using new hardware for the first time to build a unique BSP - a very slow and expensive procedure where few software debug tools are available. JTAG or other N-wire run-control devices can be used with an operating system vendor’s debugger in some cases when a robust BSP is not already available. Silicon vendors and I/O device vendors can leverage this technical marketing strategy too.

I encourage Microsoft and embedded Linux communities to consider improving their BSP strategy to deliver more value from a separate BSP structure too. I also encourage my readers to go ahead and submit comments to this blog post if you know of other vendors with good BSP designs as the marketplace is always changing.

View #1: A BSP is the kernel’s interface to device drivers

A VxWorks Board Support Package provides a standardized interface between hardware and the operating system. A BSP does not directly access hardware. Although a BSP does provide an interface to device drivers which in turn allows the kernel to communicate with the hardware’s assets such as device controllers, the microprocessor (CPU), memory, internal and external busses.

Figure 2 - BSP is an interface between kernel and hardware

Figure 2 demonstrates how VxWorks and the developer’s application software remain hardware independent while the BSP provides an interface to the embedded system’s architecture and hardware assets. Wind River BSPs conform to a standard, introduced with VxWorks BSP Version 1.1. The standard is fully described in the Tornado BSP Developer’s Kit for VxWorks. The BSP provides a common application programming interface (API) and a stable environment for the real-time operating system. The standard interface defines both BSP conventions and BSP validation procedures.

Wind River provides a standardized BSP validation procedure for engineers who are developing their own BSP’s. Validation is very efficient with a BSP designed for VxWorks because the BSP testing can be performed without having to test the operating system at the same time. Unlike Wind River’s real-time operating systems, most operating systems can not separate the testing of the BSP from the testing of the operating system itself making code coverage during testing a much larger and more inaccurate process. The BSP validation test suite provided by Wind River is repeatable and as such can be performed by the company developing a BSP as well as by others because of this standard. When I supported Wind River’s partners back in 2002, a partner could request that the WindLink partner program grant “Tornado Certified” status to a new BSP after passing the validation procedure as part of an overall certification process.

The validation procedure include tests for:
• Package validation
• Installation tests
• Functional tests
• Code review process including certification from the WindLink partner program

The Tornado BSP standard included conventions to be used by developers that fall into four main categories:
• Coding Conventions
• Documentation guidelines
• BSP Packaging
• Driver guidelines

Another strength of VxWorks is that it provides a high degree of architectural and hardware independence for application code because of this API. Application code and VxWorks can both more easily migrate from one architecture to an other because the BSP and related device drivers offer a consistent interface and modular design.

To further illustrate the BSP’s ability to interface hardware to software: Consider the process of laying carpet on your home’s floor. The carpet layer uses two-sided sticky tape to quickly attach just about any style carpet to any architectural floor plan beneath it. The BSP acts like this two-sided sticky tape attaching the embedded hardware to the operating system that uses it.

View #2: A BSP is a set of libraries offering a hardware abstraction layer to the kernel

The BSP enforces a modular design by isolating hardware-specific functionally into a set of libraries that provide an identical software interface to the hardware functions available on an embedded system. See detailed description of some of the common libraries and related files later in this blog post.

Figure 3 - Location of BSP files

Figure 3 shows an example of the typical files supporting a PowerPC target’s BSP and their location in a Tornado installation on a host computer such as Windows XP.

The BSP includes facilities for hardware initialization when power is first applied or when a hardware reset has been initiated. The BSP also includes support for interrupt handling and generation, hardware clock and timer management, and mapping of available local and bus memory. These basic services provide the real-time kernel with multi-tasking services and memory space for the designer’s application code.

Other device drivers and related support services can be included in this set of libraries extending the hardware abstraction to support the embedded system’s custom hardware services. These services would include networking, security, storage, graphics, and input/output to the outside world - for example. The devices referenced by the BSP can be located on a single board computer, a system on a chip (SoC), or on peripheral devices located across a wireless boundary or on a backplane using a hardware bus.

View #3: A BSP supports a host/target cross development environment

The BSP provides support for developers using Tornado tools on a host computer for engineering development such as an editor, compiler, linker, and debugger through a client/server communications protocol between the developer’s host computer and the embedded target’s CPU, hardware devices and on-board memory. For VxWorks developers, the BSP offers an interface to the WDB agent that provides an open standard for cross-hosted programming on a specific target’s architecture. The host computer supports these services using the Tornado tool suite through a target server acting as the communications agent. The target BSP can support a networked development environment using one or more of the following devices: Ethernet, JTAG, serial UART, ROM socket, or custom driver, to communicate with the host’s target server. When an application is complete and the embedded device is ready for production, the WDB agent can be removed from the target’s BSP.

Figure 4 - BSP supports host/target cross development

Figure 4 demonstrates a typical cross development embedded programming model. The WDB client on the target BSP communicates with the host’s target server. This host/target pair supports connecting other software and hardware tools that lower the cost of a typical engineering cycle: design, edit, compile, link, download, debug, test, and deploy.

There are advantages to having a BSP that is separated from the kernel….

A BSP allows target applications to be ported to many architectures.

The three views of a BSP described above are all consistent with today’s engineering needs for a common interface to development tools residing on a robust host computer in support of an embedded application requiring operating system support and services that is modular and portable across many different architectures.

Wind River and its board and silicon partners offer a wide variety of BSP’s for custom off the shelf (COTS) single board computers, and time saving reference designs on more than 12 different architectures. See the BSP web site I designed for Wind River back in 2002:

www.windriver.com/products/bsp_web/bsp_architecture.html

Description of BSP technical features

There usually is a file named target.nr defined in the BSP documentation standards for each BSP. The file contains a list of technical features supported and unsupported for a particular COTS or reference board. The list of features describes what a BSP is expected to do during hardware initialization when the CPU executes its first instructions as well as what hardware assets should be presented to the operating system. This information is summarized here.

Boot Monitor
• Describe the methods and devices available for booting RTOS on this board. (sm, SCSI, Ethernet, vendor-bug ROMs, open firmware, visionWARE, etc).
• Describe the network support available for booting; bootp, proxy-arp, etc…

Default Ram size
Additional supported memory options
Cache support
Flash and ROM memory
• How are ROMs made and installed? (How do they split?) Can FLASH ROMs be burned on board? If so, how?

Timer support in addition to system clock
• Describe routines that are associated with speed of CPU and Timers

Devices supported:
• The chip drivers included are:
templateSio.c - template serial driver
templateTimer.c - template timer driver
templateVme.c - template VMEbus driver
templateNvram.c - template non-volatile RAM driver
• Describe the device drivers for this board. Are there special driver ptions that must be used with this board such as CompactPCI hot swap support? Read the specific driver documentation and describe any special options used with this board.
Memory Map
• Provide a detailed memory map of the local bus, and all additional busses from a bus master point of view. Identify only slave devices actually on each bus, not their apparent address on some other bus. (i.e. if a serial device is a PCI device, do not list it on the local bus memory map, just the PCI memory map). Identify all addresses that the user can adjust by changing config.h, as being software controllable. Identify all bus master devices (DMA) on each bus.
• If VME is present, describe the default parameters for the master windows and how to change them, if possible. (master access means accessing some other board from this board). Describe the default parameters for the slave access windows, and how to change them, if possible. (Slave access means an access from another bus master). The normal VxWorks default is to enable the slave access window(s) only on CPU 0, as part of the routine sysProcNumSet(). Otherwise, slave accesses are not normally permitted.
• If PCI is present, describe the configuration access methods used to access PCI configuration space. Describe any address mapping from local addresses to PCI addresses and vice versa. Describe how the user can alter this, if appropriate.
Shared Memory
• If appropriate, identify the main bus and the type of shared memory support provided, if any. Identify the type of mailbox support and Test-And-Set support used. Identify any special support, or consideration, necessary from other boards in a multi-board system.
Interrupts
• Provide a list of interrupts/exceptions by priority and/or vector number. Describe any special interrupt connection routines or considerations used with this BSP.
Serial Ports
• Identify the default configuration for all serial ports. Document any special considerations: i.e. hardware flow control cannot be disabled thus requiring a jumper to be installed when no terminal device is connected.
SCSI Support
• Are there any known SCSI configuration limitations? Does the BSP support SCSI-1 or SCSI-2? Describe any special connectors or adapters. Does the board include terminators on-board? Is there a jumper to activate the termination network?
Ethernet Support
• Describe the Ethernet ports on the board. Identify how the MAC address is obtained or specified for each port.
Delivered Objects
• Which pre-compiled objects are delivered with the BSP?

Make Targets
• If there is any special information about a specific make target, then it should be explained. Identify any standard targets that do not build or run correctly. (bootrom, bootrom_uncmp, bootrom.res_rom, examples on VxWorks also include: vxWorks, vxWorks.st, vxWorks.res_rom, vxWorks.res_rom_nosym, vxWorks_rom).
Special routines
• Are there any unique BSP routines available to the user?
Divide by zero exception
• Describe exception handling of divide by zero event.
Host-Target Communications Support
• Name of client server agent such as WDB for VxWorks
• Describe additional WDB agents supported for debug support with host if any.

Some details on the collection of BSP libraries

BSP Source and Include Files reside in the following two subdirectories of a Tornado installation:
• TornadoBaseDirectory/target/config/all
• TornadoBaseDirectory/target/config/BSPname

See figure 2 for a view of these subdirectories and files. The subdirectory TornadoBaseDirectory /target/config/bspname contains the hardware dependent Board Support Package (BSP), which consists of files for the particular hardware used to run VxWorks, such as a CompactPCI board with specific semiconductor silicon assets for serial lines, timers, and other devices. The files include:

• Makefile
• sysLib.c
• sysSerial.c
• sysALib.s
• romInit.s
• bspname.h
• config.h

Two target-specific libraries, sysLib and sysALib, are included with each port of VxWorks. These libraries are the heart of VxWorks portability; they provide an identical software interface to the hardware functions of all boards. They include facilities for hardware initialization, interrupt handling and generation, hardware clock and timer management, mapping of local and bus memory spaces, memory sizing, and so on.

The System Library
The file sysLib.c provides the board-level interface on which VxWorks and application code can be built in a hardware-independent manner. The functions that should be addressed include:

• Initialization functions
1. Initialize the hardware to a known state
2. Identify the system

• Initialize drivers, such as SCSI or custom drivers

• Memory/address space functions
1. Get the on-board memory size
2. Make on-board memory accessible to external bus (optional)
3. Map local and bus address spaces
4. Enable/disable cache memory
5. Set/get nonvolatile RAM (NVRAM)
6. Define the board’s memory map (optional)
7. virtual-to-physical memory map declarations for processors with MMUs

• Bus interrupt functions
1. Enable/disable bus interrupt levels
2. Generate bus interrupts

• Clock/timer functions
1. enable/disable timer interrupts
2. set the periodic rate of the timer

• Mailbox/location monitor functions (optional)
1. Enable mailbox/location monitor interrupts

The sysLib library does not support every feature of every board: some boards may have additional features, others may have fewer, others still may have the same features with a different interface. For example, some boards provide some sysLib functions by means of hardware switches, jumpers, or PALs, instead of by software-controllable registers.

The configuration modules usrConfig.c and bootConfig.c in TornadoBaseDirectory/target/config/all subdirectory are responsible for invoking this library’s routines at the appropriate time. Device drivers can use some of the memory mapping routines and bus functions.

Each BSP also includes a boot ROM or other boot mechanism. Many of these import the run-time image from the development host. For information on boot ROMs and other booting mechanisms see Tornado Getting Started manual and VxWorks User ’s Guide section 8.9 Creating Bootable Applications. For information on target-specific libraries, see 8.2 The Board Support Package (BSP) in the VxWorks User’s Guide and the target-specific reference entries for your board type starting with the file target.nr on the BSP distribution.

Virtual Memory Mapping
For boards with MMU support, the data structure sysPhysMemDesc defines the virtual-to-physical memory map. This table is typically defined in sysLib.c, although some BSPs place it in a separate file, memDesc.c. It is declared as an array of the data structure PHYS_MEM_DESC. No two entries in this descriptor can overlap; each entry must be a unique memory space.

The sysPhysMemDesc array should reflect your system configuration, and you may encounter a number of reasons for changing the MMU memory map, for example: the need to change the size of local memory or the size of the VME master access space, or because the address of the VME master access space has been moved. For information on virtual memory mapping, as well as an example of how to modify sysPhysMemDesc, see VxWorks User’s Guide section 7.3 Virtual Memory Configuration.

The Serial Driver
The file sysSerial.c provides board-specific initialization for the on-board serial ports. The actual serial I/O driver is located in the TornadoBaseDirectory /target/src/drv/sio directory. The library ttyDrv uses the serial I/O driver to provide terminal operations for VxWorks.

BSP Initialization Modules
The following files initialize the BSP:

The file romInit.s contains assembly-level initialization routines.

The file sysALib.s contains initialization and system-specific assembly-level routines.

BSP Documentation
The target.nr file located in the TornadoBaseDirectory /target/config/bspname directory is the source of the online reference entries for target-specific information in our new BSP web site. For a description on how to view the target.nr reference files supplied with our product distributions, see the Tornado Getting Started manual. The target.nr file describes the supported board variations, the relevant jumpering, and supported devices. It also includes an ASCII representation of the board layout with an indication of board jumpers (if applicable) and the location of the ROM sockets.

References

• Tornado Getting Started Manual
• VxWorks User ’s Guide
• Tornado BSP Developer’s Kit for VxWorks: User’s Guide (some times referred to as a porting guide)
• Tornado BSP Training Workshop - book 1 (see Wind River training web site for BSP class times)
• Wind River’s BSP web site

The Wind River logo is a trademark of Wind River Systems, Inc., and Wind River is a registered trademark of Wind River Systems. Other marks used herein are the property of the respective owners.

Technorati Tags: Ron Fredericks, Wind River, VxWorks, Board Support Package, BSP, Tornado, FTP, Bootp, TFTP, command shell, RARP, Network Stack, JTAG, N-wire, Ethernet, JTAG, UART, ROM

Ron Fredericks writes: Engineers want to build compelling products that meet their project requirements. Corporate executives want to invest in innovative people that build products that, in turn, meet their market’s window; while, both want to stay within budget. Yet both groups may feel overwhelmed with the prospect of expressing the very heart of their inspiration at some critical times during the life of these projects. In today’s post, I try to address this issue from the engineer’s perspective reaching out to the financial decision makers that ultimately control the purse strings of every project.

Table of Contents

Introducing Financial-Speak to Engineers
ROI Example: Embedded Linux
Evaluating Incremental Cash Flows
ROI Example: Simple Project Comparisons Using Net Present Value
ROI Example: Evaluating an Infrastructure Project
ROI Example: The Original Design Manufacturer
References
Errors and Changes Planned for this Blog Post

Introducing Financial-Speak to Engineers

In a previous post I introduced the idea that ethics might be the common framework between this dichotomy in communication between engineers, marketers, and executives. In this post, I suggest that engineers might apply this ethical approach by taking some time out to learn the language of business development from a financial management perspective - a conversational framework suitable for an interdisciplinary team concerned with engineering risk and strategic business value, but expressed using financial definitions.

The term Return On Investment (ROI) can be used for all three disciplines: engineering, marketing, and finance. ROI is just vague enough to cover most any discussion an engineer may encounter through-out the life of a project: from the initial decision to fund your project, to evaluating change requests during the design, build, test, and deployment cycle of an ongoing project. Evaluating ROI from a financial perspective is an ethical approach to decision-making because the financial terms I promote for this ethical framework have very precise meanings. So precise in fact, that I too have had to go back and rewrite several sections of this blog post thanks to One Nomad’s Blog comments received in this blog’s first posting.

It was the lack of financial precision embedded within my first draft for this blog post which my guest reader used to convince me of my own mistakes. Yet to be clear, identifying my mistake is also my gain. Effective communication is a process of two or more people sharing ideas…

Learning to converse and plan using financial terms for ROI decision-making can level the playing field between engineers, marketers, and business executives since ROI itself is not a common financial term. Engineers practicing Financial-Speak centered around ROI as the goal, can help reduce many of the common problems related to individuals trying their best to participate in team decision making. This leveling of the playing field - between team members - can also enhance the power of their conversation, leading the way for the much sought after innovations that are in popular demand today.

Consider building a financial model around ROI before presenting your most important technical needs to executives, marketers, and other decision makers. Read on to learn how. Of course ROI from a financial perspective is not the only way to build effective interdisciplinary teams with engineers involved. In a future post I may suggest a corollary to this ethical approach for executives and marketers who would like to reach out to engineers – using Six Sigma, CMMI, and emerging techniques developed by Dr. Thomas J. Buckholtz as useful processes seeped in ROI terminology.

Figure 1: Net Present Value Equation

Where:
is the Net Present Value function, in dollars
is a project’s Cash Flow, in dollars
is the hurdle Rate, in percent per period
is the Initial Investment (a negative number), in dollars
And:
is the cash flow’s time increment, or period
is the total number of cash flow periods for
Time increment for and might be in years, quarters, or months, for example

ROI Example: NPV’s Effect on Embedded Linux

The equation in Figure 1 forms the heart of my “ethics in engineering” proposal. Namely, the sooner a new device gets to market, the sooner a firm can realize new income. New income realized sooner, is much better than income realized later. A finance discussion around NPV would call this time’s negative impact on the value of money. I’m talking about the exponential effect that the prevailing interest rate, R, has in the NPV equation shown in figure 1.

A few years ago several of the leading embedded operating system suppliers used this equation to show that embedded Linux was a poor choice for new embedded device development projects. One such paper published by Dr. Jerry Krasner in 2003, Total Cost of Development, presents the typical argument pretty well. At that time Dr. Krasner and many others may have been right. Now in 2007, times have changed significantly. A recent blog entry on CNET shows the missing element from Dr. Krasner’s report and is a Harold for the embedded industry going forward: Oracle touts Linux deals.

How times have changed…

Because of the significant adoption of Linux in enterprise projects, the total project cost of using embedded Linux has gone down too. Indeed, the migration and reuse of enterprise Windows operating system application programming interfaces (API’s), kernel components, and development tools into embedded device projects was a key part of Dr. Krasner’s report, see link above. Dr. Krasner concluded at the time that embedded Windows CE made the best choice for new projects from a total cost of ownership perspective - just another way of looking at NPV!

Now the ROI benefits behind projects that select embedded Linux follows Dr. Krasner’s logic perfectly. Embedded Linux is now experiencing the same reduced total cost of ownership that only embedded Windows CE enjoyed just a few years ago. The reduced total cost of ownership comes from new and improved tools, components, and API’s that cross over from enterprise projects to the embedded marketplace. There is a significant overlap in Linux kernel updates, components, and tools driven by enterprise projects that are also suitable for use in embedded projects.

The available pool of engineers that know how to work with Linux can now support embedded development projects that use embedded Linux too. The marketing movement around the value and excitement of using Linux may also reduce the cost of taking an embedded device to market. In short: lower upfront costs, more options, more solutions, and faster time to market. Even Dr. Krasner has decided to post an update to his old white paper showing total cost of development to be favorable for embedded Linux projects. Download his updated paper.

None of these enterprise driven benefits exist with respect to the traditional embedded real-time operating system (RTOS). To be clear, there are other benefits to using an RTOS. I discuss one significant benefit to using an RTOS in another post: How to Leverage the Value of a Board Support Package.

Evaluating a Project’s Incremental Cash Flow

NPV is just one example of applying the principle of ROI to making project decisions. NPV falls into the general category of capital budgeting, a process of evaluating proposed investments into new projects. The capital budgeting process is concerned only with incremental cash flows. So the vague concept of ethics can be transformed into a specific financial discussion.

Two financial functions can measure time’s effect on money:

(1) Net Present Value (NPV) expressed as a monetary value,
and

(2) Internal Rate of Return (IRR) expressed as a percentage.

Where:

Net Present Value (NPV) of a capital budgeting project is the dollar amount of change in the value of the firm as a result of undertaking the project [Ref: Financial Management: Principles and Practice P.234]. The mathmatic definition for NPV is:

NPV = IV + Sum[ CF(k) / (1+R)^k ], k ranges from 1 to N

Where:

IV = Initial Investment (a negative number)
CF(k) = cash flow value (project outputs - project inputs) for period k
R = hurdle rate per period
period = a unit of time, typically year, quarter, or month
N = total number of periods for the project

Present Value (PV) is the value today of a future, or expected, cash flow. The mathematic definition for PV is:

PV = Sum[ CF(k) / (1+R)^k ], k ranges from 1 to N

NPV can be expressed in termis of its present value (PV):

NPV = IV + PV

Hurdle Rate is the required rate of return before launching a new project. The hurdle rate must be carefully chosen. It can be expressed as a percent per period. The period is commonly defined as one year, but other convenient time period could be selected such as one quarter, or one month. The same unit of time will need to be associated with cash flow. Other rate terms can be used in addition to, or instead of, hurdle rate: discount rate, cost of capital, or interest rate.

Internal Rate of Return (IRR) is the discount rate at which the
NPV of the project is zero. [Ref: Financial Management: Principles and Practice P.240]. The mathematic definition for IRR is related to NPV:

0 = IV + Sum[ CF(k) / (1+IRR)^k ], k ranges from 1 to N

NPV and IRR are related to each other:
What follows is a list of relationships between NPV and IRR. Use these relationships after calculating the NPV and IRR for each of the proposed project alternatives.

(1) If NPV(CF,R, IV) = 0,
then the hurdle rate, R = IRR

(2) For any set of cash flows estimated for a prospective project,
there is only one value for NPV.
But, the same project model can result in several IRR values,
where NPV = 0.

(3) If IRR > Hurdle Rate,
then a prospective project may make an acceptable
investment.

(4) If IRR >> Hurdle Rate (i.e. significantly greater than),
then a prospective project may carry too much risk.

(5) The hurdle rate includes both a minimum desired rate
of return for a project, and a threshold representing risk.
(5-a) A typical hurdle rate for an E-Business project
might be 15%.
(5-b) A typical hurdle rate for an embedded systems project
might be 18%.
(5-c) Embedded Components, Inc. is focused on lowering risk
for its members by promoting the re-use of pre-existing
components through its online marketplace
for embedded device manufacturers and their
communities.

(6) In general seek to maximize NPV, not IRR.

(7) Yet, if two projects have NPV curves that cross over each
other,
then the interest R where the curves cross is called
the Crossover Point.
(7-a) If the Crossover Point > IRR,
then accept the project with higher NPV.
(7-b) If the Crossover Point < IRR,
then accept the project with higher IRR.

(8) An NPV value of zero also means the investment into that
project would neither gain nor loose value for the company.

Define a project’s return on investment (ROI):

1a) Profitability Index (PI), measured in % percent

1b) Open Source Profitability Index (PI_FOSS)

2a) Payback Period (PP), measured in time such as years, quarters or months

2b) Open Source Payback Period (PP_FOSS)

3) Sensitivity Analysis, a plot of NPV verses Interest Rate

Return on Investment (ROI) is a business case analysis concerned with the net financial impact associated with a set of costs and benefits. Most research around capital budgeting does not define a specific calculation associated with ROI. Unlike NPV and IRR, which use formulas generally agreed to by industry, ROI calculations can be industry specific. I found an excellent overview of ROI in a paper by Dr. Jeffery [Ref: Return on Investment Analysis for E-Business Projects equation 6, page 6]. In his paper Dr. Jeffery presents a definition for ROI as:

ROI = 100% x (Project Outputs - Project Inputs) / (Project Inputs)

Where:

Project Outputs represent the value created by a project such as new income generated, efficiency gains, cost savings from improved internal processes, new intellectual property created, and strategic benefits (such as increased marketshare, brand name recognition, incremental gains in product mix, and improved vendor relationships).

Project Inputs represent expenses related to a project such as the initial investment in software and tools, development costs (such as professional employee salaries), facilities expenses (including building depreciation, grounds maintenance, service level agreements, and equipment depreciation,) deployment costs (such as sales commissions, marketing, shipping, and 3′rd party software run-time fees), goernment fees (such as sales taxes, patent filings, and corporate governance), and legal fees.

The sections below are under re-construction as of 3/3/08

Profitability Index (PI):

PI adjusted for Free and Open Source Software (PI_FOSS):

So one of several projects under consideration to fund, may be the most acceptable if its NPV is a large enough positive number. In other words, a project is acceptable if the IRR is greater than or equal to the hurdle rate. Where the hurdle rate is defined as the expected rate of return on a potential investment that a manager demands before investing his or her money into a project. I have seen hurdle rates in the range of 8% to 18%, for example.

Measuring the risk of a capital budgeting project can be done by calculating the coefficient of variation (CV) on the expected returns from a firm’s asset portfolio with and without the new project being undertaken. Since the CV is defined as the ratio of the standard deviation to the mean, it can be used to determine how much volatility (risk) will be assumed in comparison to the amount of return expected from the proposed project.

There are several wrinkles in the capital budgeting decision process to consider:
(1) Non-simple projects,
(2) Projects that have multiple IRRs,
(3) Comparison of projects with unequal project lives, and
(4) Strategic benefits.

Read on to learn how to manage the financial data behind project proposals with all 4 of these complicating factors taken into account.

ROI Example: Project Comparisons Using Financial Terms

I developed a MathCad program to compare and plot two projects based on several financial terms. The MathCad equations can be used if you already have this math package. Download the MathCad template [tbd]

If you prefer to use Microsoft’s Excel, an open source office package, or google’s hosted office suite, then you can use the equations I develop here to handle the calculations.

In this Mathcad example, two projects with the same basic financial data are compared. Project A is a typical project with estimated sales (as a result of project completion) that builds up over time. Project B is not typical, but is a good test case. Project B uses equal payback amounts over time - similar to an annuity.

Define Initial Data for Two Projects

Time, N (in years)

Initial Investment, IV, in $ dollars

Interest Rate, Rate, in % percent

Cash Flow, CF, in $ dollars

Define Equations

Net Present Value, NPV, in $ dollars

Present Value, PV, in $ dollars

Coefficient of Variation, CV

Return On Investment, ROI

Compare Results for the Two Projects

Results for project A

Results for project B

Plot of Projects Over a Span of Rates

Discussion

The plot of NPV vs. Rate shows that if the Rate is zero, the NPV for both projects are the same. The plot also shows that the hurdle rate must be set much lower for Project A to be approved by a firm’s finance team in comparison to project B (looking at NPV equal to zero in the graph). Yet project B is not a likely outcome either because the sales forecasts aren’t realistic. Therefore the features and benefits of project A could be re-evaluated such that estimated sales over time increases enough to outweigh the initial lag in projected sales - to make up for the time-cost of money burden.

ROI Example: Evaluating an Infrastructure Project

I like this example even though it is far from embedded device projects. It provides a solution to the comparison between project choices that go beyond just simple cash flow. It points out that the process of getting to an ROI number can be more important to the success of some projects than the number itself.
Beyond ROI … Justifying a Business Intelligence Initiative, Digital Review Magazine, January 2004, Thomas Groh

ROI Example: The Original Design Manufacturer

An ODM is a good reference point for engineers and executives alike in the embedded systems industry. An ODM is a design to manufacture house, often located in Taiwan, People’s Republic of China (PRC), or Singapore. These companies work with their local silicon vendors and other regional suppliers to keep themselves informed of what tools, application frameworks, middleware, and silicon that may work together for various projects they are considering. To be clear, these local component vendors are integral partners for the ODM - right where the parts are often made. The ODM then has many advantages with respect to cash flow and its associate time-cost of money: lowest possible cost for parts, improved supply chain advantage without the need to pre-purchase in bulk, lower cost of knowledge, and cheaper labor costs. The ODM also focuses on the engineering effort rather than the marketing, brand recognition, and product sales efforts that their OEM (original equipment manufacturer) clients face. The goal of the ODM is to design cool stuff and manufacture all or part of the final product for its OEM client.

Figure 2: Sample Financial Spreadsheet

In Figure 2 above, I show a sample spreadsheet that would be a typical tool used by an ODM and its OEM client. How much should an ODM project cost? Take a look at the bottom line. For this project, the ODM figures on a shared IRR of 43% over an 8 year time line (only 5 of the 8 years are shown in Figure 2) using this set of numbers. A rate of return higher than most any hurdle rate. As a result, the OEM client may find funding this project to be attractive (remember that the OEM will have to factor in brand, marketing, and sales costs). The 8-year time line in this example may be too long for some projects. You can download a working copy of this cash-flow spreadsheet or their task-based budget spreadsheet from Bird Foundation’s web site and use any time-line you like for your next project.

Take a look at lines D, for development expenses, and C, for capital expenses. These two lines are where the operating system, development tool, and component vendors live. The cost of engineering and project management charged by the ODM lives here too.

The Bird Foundation
It is interesting to take note of the software tools and operating system choices available to the ODM. These are some of the only components that are not designed and built in or near the ODM’s location. Does Microsoft Windows CE make a better choice, or Wind River’s VxWorks, or should an embedded Linux version be the bases for development tools on this project? Well it all depends. Flexing the financial estimates for these two lines D and C are often a point of significant debate for a sales team or a roll-your-own internal engineering team. In this case, startup and recurring costs are important. Time to market is another point of consideration - here again the time-cost of your firm’s monetary assets will come into play. I invite sales and engineering teams to study the other numbers on this sample spreadsheet and envision how their product or service value might affect the final calculation of IRR. There can be further discussion on the effect of each financial component with respect to your position - there is likely no single right or wrong answer. One ROI strategy for embedded components and tools software vendors is to consider building more relationships with an ODM’s trusted local hardware component suppliers.

So where can you get more information on this spreadsheet? The answer can be found with the Bird Foundation. A grant giving organization that focuses on building engineering relationships between Israeli companies and OEM companies in United States - who in-turn may include an ODM partner. The spreadsheet example in Figure 2 comes right out of their guidelines for financial and project management (see Proposal Preparation Guidelines page 28). I invite you to learn more about this foundation, how it may work in developing technical partnerships with international companies you can leverage; and their great guidelines offered on the Bird foundation web site. Indeed this is a great example of using ROI as an ethical framework between partner companies from a global perspective.

References

This section under construction as of 12/8/07

Internal Rate of Return

Perils of the Internal Rate of Return
http://hspm.sph.sc.edu/COURSES/ECON/invest/invest.html

Text Books

Financial Management: Principles and Practice
by Timothy J. Gallagher and Joseph D. Andrew, Jr.
Copyright 1997 by prentice-Hall, Inc.

Return on Investment Analysis for E-business Projects
by Dr. Mark Jeffery, Northwestern University

The old reference section below

An overview of ROI from a sales and marketing perspective - a rich alternative perspective from the financial content on this blog post:
Customer Centric Thinking and ROI (turn your speakers on)

The Bird Foundation project guidelines, and project spreadsheets, can be reviewed and downloaded from here:
www.birdf.com/Index.asp?ArticleID=57&CategoryID=77&Page=1

A great Windows calculator (see Figure 3 below) for most of your engineering and financial needs can be downloaded from here:
www.hp41.org/LibView.cfm?Command=View&ItemID=458

The original HP financial support software module works within this simulated HP41 programmable calculator and can also be downloaded from the same site, here:
www.hp41.org/LibView.cfm?Command=View&ItemID=3

The original HP How To manual for financial decision making can be downloaded or read from this the site as well, from here:
www.hp41.org/LibView.cfm?Command=View&ItemID=445

Figure 3: The HP41 Calculator Emulated on a Windows Desktop

Next steps…

I invite you to use this blog post’s comment facility to share your experience as an engineer, innovator, sales manager, marketer, or executive. Do you think a financial vocabulary can be used to build an effective (and ethical) balance for your team between consensus and innovation?

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