Introducing 74HC193 Simulation to LTspice

Ron Fredericks writes: I have completed the design and test of a new component for LTspice/SwitchCAD III circuit simulation and schematic capture. In a previous post I discussed my interest in the 74193 presettable synchronous 4-bit binary up/down counter IC for a digital volume control circuit I am building. The circuit simulation described below focuses on how to simulate the 74HC193 IC, but timing and voltage parameters built into this design allow a designer to easily simulate other variants of this IC from high speed Si-gate CMOS HC and HCT devices to low power Schottky TTL devices.

All circuits related to this 74HC193 simulation are available here>

The 74HC193 Component

See figure 1 below for a screen shot of the completed design. The circuit was built from the digital gates in the component library supplied with the original Linear Technology’s free LTspice tool.

74HC193 Circuit and Related Components
Figure 1 – 74HC193 Circuit and Related Components

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To keep the design looking like the original data sheet logic diagram, as published by companies that include NXP Semiconductors and Texas Instruments, a custom “T notS-R FlipFlop” subcomponent and corresponding assembly file was first created. This subcomponent was reused 4 times in the main IC logic diagram. An assembly file called 74hc193.asy was also created. It includes all pins used on the commercial IC except ground and Vcc. The IC’s internal power supply is not simulated by the Linear Technologies’ gates, and so they are not used or required in this design either.

Each gate within the design has a few variables assigned to them so that the IC remains flexible and easy to reuse in new projects:

  • tdgate right td (propagation time delay assigned to each gate)
  • tdgate2 right td (propagation time delay assigned to the D FlipFlop)
  • tripdtgate right tripdt (td’s accuracy band assigned to each gate including the D FlipFlop)
  • vhighgate right logical high value for each gate and D FlipFlop
  • vlowgate right logical low value for each gate and D FlipFlop

These variables can be assigned their corresponding time and voltage values using a .param statement placed in the main circuit. These values are then within scope for automatic reuse by the 74HC193 component and flipflop subcomponent simulations. Below is an example of how parameter assignment can be made (as used in the test circuit described next):

.param tdgate=10n tdgate2=3*tdgate tripdtgate=1n vhighgate=5v vlowgate=0v

The Test Circuit

See figure 2 below for a screen shot of the completed simulation test circuit.

74HC193 Simulation Test Circuit and Truth Table Waveform Analysis
Figure 2 – 74HC193 Test Circuit and Truth Table Waveforms

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The test circuit demonstrates the use of the 74HC193 component assembly.

Individual pulse voltages are applied to the component’s input pins to validate the new device:

  • MR (asynchronous master reset) right pulsed high at the beginning and end of simulation. Unlike the waveform often shown in the 74xx193 IC’s datasheet sequence diagram (see page 7 of 29 in this version published by NXP), the second reset pulse was added to insure that Q0 to Q3 output values really do reset.
  • overline{PL} (asynchronous parallel load) right pulsed low near beginning of simulation to set flip-flop outputs (Q0 to Q3) to the data input values (D0 to D3).
  • CPU (rising edge triggered count up clock) right pulsed low several times to demonstrate both the count up behavior of the flip-flop outputs and the terminal count up, or carry, (overline{TCU}) output.
  • CPD (rising edge triggered count down clock) right pulsed low several times to demonstrate both the count down behavior of the flip-flop outputs and the terminal count down, or borrow, (overline{TCD}) output.
  • D0 to D3 (data input pins) right tied to either logic-high or logic-low for this simulation. The logic-low is constructed from a zero voltage component instead of simply being tied to the LTspice global circuit common node (ground). This is because of the LTspice gate component’s special behavior in removing the simulation of individual gate pins tied to the common node ground.

All voltage sources are referenced using the same high and low voltages described in the previous section: vhighgate and vlowgate. These values can be reassigned to all gates, all at once, using the .param statement discussed above.

Download the Circuits

The 74HC193 component, subcomponent, assemblies, test circuits, and plot control files can all be downloaded without restriction in their use. The datasheet supplied does have some licensed use restrictions, as defined in its last page. The reference to the 74HC193 data sheet from NXP Semiconductors is in no way an endorsement of the company or its products, but it is the most recent and best documented behavior for this device that I have found.

  1. 74hc193.74hct193.pdf 74HC193 data sheet published by NXP Semiconductors in Adobe Acrobat PDF format
  2. 74HC193_test.asc test circuit as shown in figure above
  3. 74HC193_test.plt plot control file used by the test circuit above
  4. 74HC103_test2.asc debug circuit used to debug errors in original design
  5. 74HC103_test2.plt plot control file used by the test2 circuit above
  6. 74HC193.asc circuit component
  7. 74HC193.asy circuit component assembly used in the test circuit above
  8. TnotSRFlipFlopFromD.asc circuit subcomponent used by 74HC193.asc file above
  9. TnotSRFlipFlopFromD.asy circuit subcomponent used by 74HC193.asc file above
  10. The screenshots saved as png files – as shown in this blog post
  11. readme.txt text file granting a license to use the 74HC193 simulation files listed above without restriction and without warranty

Download the files listed above for your LTspice designs all in one zipped directory.

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